/*
 *  Licensed to the Apache Software Foundation (ASF) under one or more
 *  contributor license agreements.  See the NOTICE file distributed with
 *  this work for additional information regarding copyright ownership.
 *  The ASF licenses this file to You under the Apache License, Version 2.0
 *  (the "License"); you may not use this file except in compliance with
 *  the License.  You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 *  Unless required by applicable law or agreed to in writing, software
 *  distributed under the License is distributed on an "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the License for the specific language governing permissions and
 *  limitations under the License.
 */
/** 
 * @author Intel, Evgueni Brevnov
 * @version $Revision: 1.1.2.1.4.3 $
 */  


#ifndef _INST_ID_H
#define _INST_ID_H


#ifndef __cplusplus

typedef enum Inst_id_e
{
EM_INST_NONE = 0,
EM_ILLOP = EM_INST_NONE,
EM_IGNOP,
EM_ADD_R1_R2_R3,
EM_ADD_R1_R2_R3_1,
EM_SUB_R1_R2_R3,
EM_SUB_R1_R2_R3_1,
EM_ADDP4_R1_R2_R3,
EM_AND_R1_R2_R3,
EM_ANDCM_R1_R2_R3,
EM_OR_R1_R2_R3,
EM_XOR_R1_R2_R3,
EM_SHLADD_R1_R2_COUNT2_R3,
EM_SHLADDP4_R1_R2_COUNT2_R3,
EM_SUB_R1_IMM8_R3,
EM_AND_R1_IMM8_R3,
EM_ANDCM_R1_IMM8_R3,
EM_OR_R1_IMM8_R3,
EM_XOR_R1_IMM8_R3,
EM_ADDS_R1_IMM14_R3,
EM_ADDP4_R1_IMM14_R3,
EM_ADDL_R1_IMM22_R3,
EM_CMP_LT_P1_P2_R2_R3,
EM_CMP_LTU_P1_P2_R2_R3,
EM_CMP_EQ_P1_P2_R2_R3,
EM_CMP_LT_UNC_P1_P2_R2_R3,
EM_CMP_LTU_UNC_P1_P2_R2_R3,
EM_CMP_EQ_UNC_P1_P2_R2_R3,
EM_CMP_EQ_AND_P1_P2_R2_R3,
EM_CMP_EQ_OR_P1_P2_R2_R3,
EM_CMP_EQ_OR_ANDCM_P1_P2_R2_R3,
EM_CMP_NE_AND_P1_P2_R2_R3,
EM_CMP_NE_OR_P1_P2_R2_R3,
EM_CMP_NE_OR_ANDCM_P1_P2_R2_R3,
EM_CMP4_LT_P1_P2_R2_R3,
EM_CMP4_LTU_P1_P2_R2_R3,
EM_CMP4_EQ_P1_P2_R2_R3,
EM_CMP4_LT_UNC_P1_P2_R2_R3,
EM_CMP4_LTU_UNC_P1_P2_R2_R3,
EM_CMP4_EQ_UNC_P1_P2_R2_R3,
EM_CMP4_EQ_AND_P1_P2_R2_R3,
EM_CMP4_EQ_OR_P1_P2_R2_R3,
EM_CMP4_EQ_OR_ANDCM_P1_P2_R2_R3,
EM_CMP4_NE_AND_P1_P2_R2_R3,
EM_CMP4_NE_OR_P1_P2_R2_R3,
EM_CMP4_NE_OR_ANDCM_P1_P2_R2_R3,
EM_CMP_GT_AND_P1_P2_R0_R3,
EM_CMP_GT_OR_P1_P2_R0_R3,
EM_CMP_GT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_LE_AND_P1_P2_R0_R3,
EM_CMP_LE_OR_P1_P2_R0_R3,
EM_CMP_LE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_GE_AND_P1_P2_R0_R3,
EM_CMP_GE_OR_P1_P2_R0_R3,
EM_CMP_GE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_LT_AND_P1_P2_R0_R3,
EM_CMP_LT_OR_P1_P2_R0_R3,
EM_CMP_LT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_GT_AND_P1_P2_R0_R3,
EM_CMP4_GT_OR_P1_P2_R0_R3,
EM_CMP4_GT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_LE_AND_P1_P2_R0_R3,
EM_CMP4_LE_OR_P1_P2_R0_R3,
EM_CMP4_LE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_GE_AND_P1_P2_R0_R3,
EM_CMP4_GE_OR_P1_P2_R0_R3,
EM_CMP4_GE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_LT_AND_P1_P2_R0_R3,
EM_CMP4_LT_OR_P1_P2_R0_R3,
EM_CMP4_LT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_LT_P1_P2_IMM8_R3,
EM_CMP_LTU_P1_P2_IMM8_R3,
EM_CMP_EQ_P1_P2_IMM8_R3,
EM_CMP_LT_UNC_P1_P2_IMM8_R3,
EM_CMP_LTU_UNC_P1_P2_IMM8_R3,
EM_CMP_EQ_UNC_P1_P2_IMM8_R3,
EM_CMP_EQ_AND_P1_P2_IMM8_R3,
EM_CMP_EQ_OR_P1_P2_IMM8_R3,
EM_CMP_EQ_OR_ANDCM_P1_P2_IMM8_R3,
EM_CMP_NE_AND_P1_P2_IMM8_R3,
EM_CMP_NE_OR_P1_P2_IMM8_R3,
EM_CMP_NE_OR_ANDCM_P1_P2_IMM8_R3,
EM_CMP4_LT_P1_P2_IMM8_R3,
EM_CMP4_LTU_P1_P2_IMM8_R3,
EM_CMP4_EQ_P1_P2_IMM8_R3,
EM_CMP4_LT_UNC_P1_P2_IMM8_R3,
EM_CMP4_LTU_UNC_P1_P2_IMM8_R3,
EM_CMP4_EQ_UNC_P1_P2_IMM8_R3,
EM_CMP4_EQ_AND_P1_P2_IMM8_R3,
EM_CMP4_EQ_OR_P1_P2_IMM8_R3,
EM_CMP4_EQ_OR_ANDCM_P1_P2_IMM8_R3,
EM_CMP4_NE_AND_P1_P2_IMM8_R3,
EM_CMP4_NE_OR_P1_P2_IMM8_R3,
EM_CMP4_NE_OR_ANDCM_P1_P2_IMM8_R3,
EM_PADD1_R1_R2_R3,
EM_PADD2_R1_R2_R3,
EM_PADD4_R1_R2_R3,
EM_PADD1_SSS_R1_R2_R3,
EM_PADD2_SSS_R1_R2_R3,
EM_PADD1_UUU_R1_R2_R3,
EM_PADD2_UUU_R1_R2_R3,
EM_PADD1_UUS_R1_R2_R3,
EM_PADD2_UUS_R1_R2_R3,
EM_PSUB1_R1_R2_R3,
EM_PSUB2_R1_R2_R3,
EM_PSUB4_R1_R2_R3,
EM_PSUB1_SSS_R1_R2_R3,
EM_PSUB2_SSS_R1_R2_R3,
EM_PSUB1_UUU_R1_R2_R3,
EM_PSUB2_UUU_R1_R2_R3,
EM_PSUB1_UUS_R1_R2_R3,
EM_PSUB2_UUS_R1_R2_R3,
EM_PAVG1_R1_R2_R3,
EM_PAVG2_R1_R2_R3,
EM_PAVG1_RAZ_R1_R2_R3,
EM_PAVG2_RAZ_R1_R2_R3,
EM_PAVGSUB1_R1_R2_R3,
EM_PAVGSUB2_R1_R2_R3,
EM_PCMP1_EQ_R1_R2_R3,
EM_PCMP2_EQ_R1_R2_R3,
EM_PCMP4_EQ_R1_R2_R3,
EM_PCMP1_GT_R1_R2_R3,
EM_PCMP2_GT_R1_R2_R3,
EM_PCMP4_GT_R1_R2_R3,
EM_PSHLADD2_R1_R2_COUNT2_R3,
EM_PSHRADD2_R1_R2_COUNT2_R3,
EM_PMPYSHR2_R1_R2_R3_COUNT2,
EM_PMPYSHR2_U_R1_R2_R3_COUNT2,
EM_PMPY2_R_R1_R2_R3,
EM_PMPY2_L_R1_R2_R3,
EM_MIX1_R_R1_R2_R3,
EM_MIX2_R_R1_R2_R3,
EM_MIX4_R_R1_R2_R3,
EM_MIX1_L_R1_R2_R3,
EM_MIX2_L_R1_R2_R3,
EM_MIX4_L_R1_R2_R3,
EM_PACK2_USS_R1_R2_R3,
EM_PACK2_SSS_R1_R2_R3,
EM_PACK4_SSS_R1_R2_R3,
EM_UNPACK1_H_R1_R2_R3,
EM_UNPACK2_H_R1_R2_R3,
EM_UNPACK4_H_R1_R2_R3,
EM_UNPACK1_L_R1_R2_R3,
EM_UNPACK2_L_R1_R2_R3,
EM_UNPACK4_L_R1_R2_R3,
EM_PMIN1_U_R1_R2_R3,
EM_PMAX1_U_R1_R2_R3,
EM_PMIN2_R1_R2_R3,
EM_PMAX2_R1_R2_R3,
EM_PSAD1_R1_R2_R3,
EM_MUX1_R1_R2_MBTYPE4,
EM_MUX2_R1_R2_MHTYPE8,
EM_PSHR2_R1_R3_R2,
EM_PSHR4_R1_R3_R2,
EM_SHR_R1_R3_R2,
EM_PSHR2_U_R1_R3_R2,
EM_PSHR4_U_R1_R3_R2,
EM_SHR_U_R1_R3_R2,
EM_PSHR2_R1_R3_COUNT5,
EM_PSHR4_R1_R3_COUNT5,
EM_PSHR2_U_R1_R3_COUNT5,
EM_PSHR4_U_R1_R3_COUNT5,
EM_PSHL2_R1_R2_R3,
EM_PSHL4_R1_R2_R3,
EM_SHL_R1_R2_R3,
EM_PSHL2_R1_R2_COUNT5,
EM_PSHL4_R1_R2_COUNT5,
EM_POPCNT_R1_R3,
EM_SHRP_R1_R2_R3_COUNT6,
EM_EXTR_U_R1_R3_POS6_LEN6,
EM_EXTR_R1_R3_POS6_LEN6,
EM_DEP_Z_R1_R2_POS6_LEN6,
EM_DEP_Z_R1_IMM8_POS6_LEN6,
EM_DEP_R1_IMM1_R3_POS6_LEN6,
EM_DEP_R1_R2_R3_POS6_LEN4,
EM_TBIT_Z_P1_P2_R3_POS6,
EM_TBIT_Z_UNC_P1_P2_R3_POS6,
EM_TBIT_Z_AND_P1_P2_R3_POS6,
EM_TBIT_NZ_AND_P1_P2_R3_POS6,
EM_TBIT_Z_OR_P1_P2_R3_POS6,
EM_TBIT_NZ_OR_P1_P2_R3_POS6,
EM_TBIT_Z_OR_ANDCM_P1_P2_R3_POS6,
EM_TBIT_NZ_OR_ANDCM_P1_P2_R3_POS6,
EM_TNAT_Z_P1_P2_R3,
EM_TNAT_Z_UNC_P1_P2_R3,
EM_TNAT_Z_AND_P1_P2_R3,
EM_TNAT_NZ_AND_P1_P2_R3,
EM_TNAT_Z_OR_P1_P2_R3,
EM_TNAT_NZ_OR_P1_P2_R3,
EM_TNAT_Z_OR_ANDCM_P1_P2_R3,
EM_TNAT_NZ_OR_ANDCM_P1_P2_R3,
EM_BREAK_I_IMM21,
EM_NOP_I_IMM21,
EM_CHK_S_I_R2_TARGET25,
EM_MOV_SPTK_B1_R2_TAG13,
EM_MOV_SPTK_IMP_B1_R2_TAG13,
EM_MOV_B1_R2_TAG13,
EM_MOV_IMP_B1_R2_TAG13,
EM_MOV_DPTK_B1_R2_TAG13,
EM_MOV_DPTK_IMP_B1_R2_TAG13,
EM_MOV_RET_SPTK_B1_R2_TAG13,
EM_MOV_RET_SPTK_IMP_B1_R2_TAG13,
EM_MOV_RET_B1_R2_TAG13,
EM_MOV_RET_IMP_B1_R2_TAG13,
EM_MOV_RET_DPTK_B1_R2_TAG13,
EM_MOV_RET_DPTK_IMP_B1_R2_TAG13,
EM_MOV_R1_B2,
EM_MOV_PR_R2_MASK17,
EM_MOV_PR_ROT_IMM44,
EM_MOV_R1_IP,
EM_MOV_R1_PR,
EM_MOV_I_AR3_R2,
EM_MOV_I_AR3_IMM8,
EM_MOV_I_R1_AR3,
EM_ZXT1_R1_R3,
EM_ZXT2_R1_R3,
EM_ZXT4_R1_R3,
EM_SXT1_R1_R3,
EM_SXT2_R1_R3,
EM_SXT4_R1_R3,
EM_CZX1_L_R1_R3,
EM_CZX2_L_R1_R3,
EM_CZX1_R_R1_R3,
EM_CZX2_R_R1_R3,
EM_LD1_R1_R3,
EM_LD1_NT1_R1_R3,
EM_LD1_NTA_R1_R3,
EM_LD2_R1_R3,
EM_LD2_NT1_R1_R3,
EM_LD2_NTA_R1_R3,
EM_LD4_R1_R3,
EM_LD4_NT1_R1_R3,
EM_LD4_NTA_R1_R3,
EM_LD8_R1_R3,
EM_LD8_NT1_R1_R3,
EM_LD8_NTA_R1_R3,
EM_LD1_S_R1_R3,
EM_LD1_S_NT1_R1_R3,
EM_LD1_S_NTA_R1_R3,
EM_LD2_S_R1_R3,
EM_LD2_S_NT1_R1_R3,
EM_LD2_S_NTA_R1_R3,
EM_LD4_S_R1_R3,
EM_LD4_S_NT1_R1_R3,
EM_LD4_S_NTA_R1_R3,
EM_LD8_S_R1_R3,
EM_LD8_S_NT1_R1_R3,
EM_LD8_S_NTA_R1_R3,
EM_LD1_A_R1_R3,
EM_LD1_A_NT1_R1_R3,
EM_LD1_A_NTA_R1_R3,
EM_LD2_A_R1_R3,
EM_LD2_A_NT1_R1_R3,
EM_LD2_A_NTA_R1_R3,
EM_LD4_A_R1_R3,
EM_LD4_A_NT1_R1_R3,
EM_LD4_A_NTA_R1_R3,
EM_LD8_A_R1_R3,
EM_LD8_A_NT1_R1_R3,
EM_LD8_A_NTA_R1_R3,
EM_LD1_SA_R1_R3,
EM_LD1_SA_NT1_R1_R3,
EM_LD1_SA_NTA_R1_R3,
EM_LD2_SA_R1_R3,
EM_LD2_SA_NT1_R1_R3,
EM_LD2_SA_NTA_R1_R3,
EM_LD4_SA_R1_R3,
EM_LD4_SA_NT1_R1_R3,
EM_LD4_SA_NTA_R1_R3,
EM_LD8_SA_R1_R3,
EM_LD8_SA_NT1_R1_R3,
EM_LD8_SA_NTA_R1_R3,
EM_LD1_BIAS_R1_R3,
EM_LD1_BIAS_NT1_R1_R3,
EM_LD1_BIAS_NTA_R1_R3,
EM_LD2_BIAS_R1_R3,
EM_LD2_BIAS_NT1_R1_R3,
EM_LD2_BIAS_NTA_R1_R3,
EM_LD4_BIAS_R1_R3,
EM_LD4_BIAS_NT1_R1_R3,
EM_LD4_BIAS_NTA_R1_R3,
EM_LD8_BIAS_R1_R3,
EM_LD8_BIAS_NT1_R1_R3,
EM_LD8_BIAS_NTA_R1_R3,
EM_LD1_ACQ_R1_R3,
EM_LD1_ACQ_NT1_R1_R3,
EM_LD1_ACQ_NTA_R1_R3,
EM_LD2_ACQ_R1_R3,
EM_LD2_ACQ_NT1_R1_R3,
EM_LD2_ACQ_NTA_R1_R3,
EM_LD4_ACQ_R1_R3,
EM_LD4_ACQ_NT1_R1_R3,
EM_LD4_ACQ_NTA_R1_R3,
EM_LD8_ACQ_R1_R3,
EM_LD8_ACQ_NT1_R1_R3,
EM_LD8_ACQ_NTA_R1_R3,
EM_LD8_FILL_R1_R3,
EM_LD8_FILL_NT1_R1_R3,
EM_LD8_FILL_NTA_R1_R3,
EM_LD1_C_CLR_R1_R3,
EM_LD1_C_CLR_NT1_R1_R3,
EM_LD1_C_CLR_NTA_R1_R3,
EM_LD2_C_CLR_R1_R3,
EM_LD2_C_CLR_NT1_R1_R3,
EM_LD2_C_CLR_NTA_R1_R3,
EM_LD4_C_CLR_R1_R3,
EM_LD4_C_CLR_NT1_R1_R3,
EM_LD4_C_CLR_NTA_R1_R3,
EM_LD8_C_CLR_R1_R3,
EM_LD8_C_CLR_NT1_R1_R3,
EM_LD8_C_CLR_NTA_R1_R3,
EM_LD1_C_NC_R1_R3,
EM_LD1_C_NC_NT1_R1_R3,
EM_LD1_C_NC_NTA_R1_R3,
EM_LD2_C_NC_R1_R3,
EM_LD2_C_NC_NT1_R1_R3,
EM_LD2_C_NC_NTA_R1_R3,
EM_LD4_C_NC_R1_R3,
EM_LD4_C_NC_NT1_R1_R3,
EM_LD4_C_NC_NTA_R1_R3,
EM_LD8_C_NC_R1_R3,
EM_LD8_C_NC_NT1_R1_R3,
EM_LD8_C_NC_NTA_R1_R3,
EM_LD1_C_CLR_ACQ_R1_R3,
EM_LD1_C_CLR_ACQ_NT1_R1_R3,
EM_LD1_C_CLR_ACQ_NTA_R1_R3,
EM_LD2_C_CLR_ACQ_R1_R3,
EM_LD2_C_CLR_ACQ_NT1_R1_R3,
EM_LD2_C_CLR_ACQ_NTA_R1_R3,
EM_LD4_C_CLR_ACQ_R1_R3,
EM_LD4_C_CLR_ACQ_NT1_R1_R3,
EM_LD4_C_CLR_ACQ_NTA_R1_R3,
EM_LD8_C_CLR_ACQ_R1_R3,
EM_LD8_C_CLR_ACQ_NT1_R1_R3,
EM_LD8_C_CLR_ACQ_NTA_R1_R3,
EM_LD1_R1_R3_R2,
EM_LD1_NT1_R1_R3_R2,
EM_LD1_NTA_R1_R3_R2,
EM_LD2_R1_R3_R2,
EM_LD2_NT1_R1_R3_R2,
EM_LD2_NTA_R1_R3_R2,
EM_LD4_R1_R3_R2,
EM_LD4_NT1_R1_R3_R2,
EM_LD4_NTA_R1_R3_R2,
EM_LD8_R1_R3_R2,
EM_LD8_NT1_R1_R3_R2,
EM_LD8_NTA_R1_R3_R2,
EM_LD1_S_R1_R3_R2,
EM_LD1_S_NT1_R1_R3_R2,
EM_LD1_S_NTA_R1_R3_R2,
EM_LD2_S_R1_R3_R2,
EM_LD2_S_NT1_R1_R3_R2,
EM_LD2_S_NTA_R1_R3_R2,
EM_LD4_S_R1_R3_R2,
EM_LD4_S_NT1_R1_R3_R2,
EM_LD4_S_NTA_R1_R3_R2,
EM_LD8_S_R1_R3_R2,
EM_LD8_S_NT1_R1_R3_R2,
EM_LD8_S_NTA_R1_R3_R2,
EM_LD1_A_R1_R3_R2,
EM_LD1_A_NT1_R1_R3_R2,
EM_LD1_A_NTA_R1_R3_R2,
EM_LD2_A_R1_R3_R2,
EM_LD2_A_NT1_R1_R3_R2,
EM_LD2_A_NTA_R1_R3_R2,
EM_LD4_A_R1_R3_R2,
EM_LD4_A_NT1_R1_R3_R2,
EM_LD4_A_NTA_R1_R3_R2,
EM_LD8_A_R1_R3_R2,
EM_LD8_A_NT1_R1_R3_R2,
EM_LD8_A_NTA_R1_R3_R2,
EM_LD1_SA_R1_R3_R2,
EM_LD1_SA_NT1_R1_R3_R2,
EM_LD1_SA_NTA_R1_R3_R2,
EM_LD2_SA_R1_R3_R2,
EM_LD2_SA_NT1_R1_R3_R2,
EM_LD2_SA_NTA_R1_R3_R2,
EM_LD4_SA_R1_R3_R2,
EM_LD4_SA_NT1_R1_R3_R2,
EM_LD4_SA_NTA_R1_R3_R2,
EM_LD8_SA_R1_R3_R2,
EM_LD8_SA_NT1_R1_R3_R2,
EM_LD8_SA_NTA_R1_R3_R2,
EM_LD1_BIAS_R1_R3_R2,
EM_LD1_BIAS_NT1_R1_R3_R2,
EM_LD1_BIAS_NTA_R1_R3_R2,
EM_LD2_BIAS_R1_R3_R2,
EM_LD2_BIAS_NT1_R1_R3_R2,
EM_LD2_BIAS_NTA_R1_R3_R2,
EM_LD4_BIAS_R1_R3_R2,
EM_LD4_BIAS_NT1_R1_R3_R2,
EM_LD4_BIAS_NTA_R1_R3_R2,
EM_LD8_BIAS_R1_R3_R2,
EM_LD8_BIAS_NT1_R1_R3_R2,
EM_LD8_BIAS_NTA_R1_R3_R2,
EM_LD1_ACQ_R1_R3_R2,
EM_LD1_ACQ_NT1_R1_R3_R2,
EM_LD1_ACQ_NTA_R1_R3_R2,
EM_LD2_ACQ_R1_R3_R2,
EM_LD2_ACQ_NT1_R1_R3_R2,
EM_LD2_ACQ_NTA_R1_R3_R2,
EM_LD4_ACQ_R1_R3_R2,
EM_LD4_ACQ_NT1_R1_R3_R2,
EM_LD4_ACQ_NTA_R1_R3_R2,
EM_LD8_ACQ_R1_R3_R2,
EM_LD8_ACQ_NT1_R1_R3_R2,
EM_LD8_ACQ_NTA_R1_R3_R2,
EM_LD8_FILL_R1_R3_R2,
EM_LD8_FILL_NT1_R1_R3_R2,
EM_LD8_FILL_NTA_R1_R3_R2,
EM_LD1_C_CLR_R1_R3_R2,
EM_LD1_C_CLR_NT1_R1_R3_R2,
EM_LD1_C_CLR_NTA_R1_R3_R2,
EM_LD2_C_CLR_R1_R3_R2,
EM_LD2_C_CLR_NT1_R1_R3_R2,
EM_LD2_C_CLR_NTA_R1_R3_R2,
EM_LD4_C_CLR_R1_R3_R2,
EM_LD4_C_CLR_NT1_R1_R3_R2,
EM_LD4_C_CLR_NTA_R1_R3_R2,
EM_LD8_C_CLR_R1_R3_R2,
EM_LD8_C_CLR_NT1_R1_R3_R2,
EM_LD8_C_CLR_NTA_R1_R3_R2,
EM_LD1_C_NC_R1_R3_R2,
EM_LD1_C_NC_NT1_R1_R3_R2,
EM_LD1_C_NC_NTA_R1_R3_R2,
EM_LD2_C_NC_R1_R3_R2,
EM_LD2_C_NC_NT1_R1_R3_R2,
EM_LD2_C_NC_NTA_R1_R3_R2,
EM_LD4_C_NC_R1_R3_R2,
EM_LD4_C_NC_NT1_R1_R3_R2,
EM_LD4_C_NC_NTA_R1_R3_R2,
EM_LD8_C_NC_R1_R3_R2,
EM_LD8_C_NC_NT1_R1_R3_R2,
EM_LD8_C_NC_NTA_R1_R3_R2,
EM_LD1_C_CLR_ACQ_R1_R3_R2,
EM_LD1_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD1_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD2_C_CLR_ACQ_R1_R3_R2,
EM_LD2_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD2_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD4_C_CLR_ACQ_R1_R3_R2,
EM_LD4_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD4_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD8_C_CLR_ACQ_R1_R3_R2,
EM_LD8_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD8_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD1_R1_R3_IMM9,
EM_LD1_NT1_R1_R3_IMM9,
EM_LD1_NTA_R1_R3_IMM9,
EM_LD2_R1_R3_IMM9,
EM_LD2_NT1_R1_R3_IMM9,
EM_LD2_NTA_R1_R3_IMM9,
EM_LD4_R1_R3_IMM9,
EM_LD4_NT1_R1_R3_IMM9,
EM_LD4_NTA_R1_R3_IMM9,
EM_LD8_R1_R3_IMM9,
EM_LD8_NT1_R1_R3_IMM9,
EM_LD8_NTA_R1_R3_IMM9,
EM_LD1_S_R1_R3_IMM9,
EM_LD1_S_NT1_R1_R3_IMM9,
EM_LD1_S_NTA_R1_R3_IMM9,
EM_LD2_S_R1_R3_IMM9,
EM_LD2_S_NT1_R1_R3_IMM9,
EM_LD2_S_NTA_R1_R3_IMM9,
EM_LD4_S_R1_R3_IMM9,
EM_LD4_S_NT1_R1_R3_IMM9,
EM_LD4_S_NTA_R1_R3_IMM9,
EM_LD8_S_R1_R3_IMM9,
EM_LD8_S_NT1_R1_R3_IMM9,
EM_LD8_S_NTA_R1_R3_IMM9,
EM_LD1_A_R1_R3_IMM9,
EM_LD1_A_NT1_R1_R3_IMM9,
EM_LD1_A_NTA_R1_R3_IMM9,
EM_LD2_A_R1_R3_IMM9,
EM_LD2_A_NT1_R1_R3_IMM9,
EM_LD2_A_NTA_R1_R3_IMM9,
EM_LD4_A_R1_R3_IMM9,
EM_LD4_A_NT1_R1_R3_IMM9,
EM_LD4_A_NTA_R1_R3_IMM9,
EM_LD8_A_R1_R3_IMM9,
EM_LD8_A_NT1_R1_R3_IMM9,
EM_LD8_A_NTA_R1_R3_IMM9,
EM_LD1_SA_R1_R3_IMM9,
EM_LD1_SA_NT1_R1_R3_IMM9,
EM_LD1_SA_NTA_R1_R3_IMM9,
EM_LD2_SA_R1_R3_IMM9,
EM_LD2_SA_NT1_R1_R3_IMM9,
EM_LD2_SA_NTA_R1_R3_IMM9,
EM_LD4_SA_R1_R3_IMM9,
EM_LD4_SA_NT1_R1_R3_IMM9,
EM_LD4_SA_NTA_R1_R3_IMM9,
EM_LD8_SA_R1_R3_IMM9,
EM_LD8_SA_NT1_R1_R3_IMM9,
EM_LD8_SA_NTA_R1_R3_IMM9,
EM_LD1_BIAS_R1_R3_IMM9,
EM_LD1_BIAS_NT1_R1_R3_IMM9,
EM_LD1_BIAS_NTA_R1_R3_IMM9,
EM_LD2_BIAS_R1_R3_IMM9,
EM_LD2_BIAS_NT1_R1_R3_IMM9,
EM_LD2_BIAS_NTA_R1_R3_IMM9,
EM_LD4_BIAS_R1_R3_IMM9,
EM_LD4_BIAS_NT1_R1_R3_IMM9,
EM_LD4_BIAS_NTA_R1_R3_IMM9,
EM_LD8_BIAS_R1_R3_IMM9,
EM_LD8_BIAS_NT1_R1_R3_IMM9,
EM_LD8_BIAS_NTA_R1_R3_IMM9,
EM_LD1_ACQ_R1_R3_IMM9,
EM_LD1_ACQ_NT1_R1_R3_IMM9,
EM_LD1_ACQ_NTA_R1_R3_IMM9,
EM_LD2_ACQ_R1_R3_IMM9,
EM_LD2_ACQ_NT1_R1_R3_IMM9,
EM_LD2_ACQ_NTA_R1_R3_IMM9,
EM_LD4_ACQ_R1_R3_IMM9,
EM_LD4_ACQ_NT1_R1_R3_IMM9,
EM_LD4_ACQ_NTA_R1_R3_IMM9,
EM_LD8_ACQ_R1_R3_IMM9,
EM_LD8_ACQ_NT1_R1_R3_IMM9,
EM_LD8_ACQ_NTA_R1_R3_IMM9,
EM_LD8_FILL_R1_R3_IMM9,
EM_LD8_FILL_NT1_R1_R3_IMM9,
EM_LD8_FILL_NTA_R1_R3_IMM9,
EM_LD1_C_CLR_R1_R3_IMM9,
EM_LD1_C_CLR_NT1_R1_R3_IMM9,
EM_LD1_C_CLR_NTA_R1_R3_IMM9,
EM_LD2_C_CLR_R1_R3_IMM9,
EM_LD2_C_CLR_NT1_R1_R3_IMM9,
EM_LD2_C_CLR_NTA_R1_R3_IMM9,
EM_LD4_C_CLR_R1_R3_IMM9,
EM_LD4_C_CLR_NT1_R1_R3_IMM9,
EM_LD4_C_CLR_NTA_R1_R3_IMM9,
EM_LD8_C_CLR_R1_R3_IMM9,
EM_LD8_C_CLR_NT1_R1_R3_IMM9,
EM_LD8_C_CLR_NTA_R1_R3_IMM9,
EM_LD1_C_NC_R1_R3_IMM9,
EM_LD1_C_NC_NT1_R1_R3_IMM9,
EM_LD1_C_NC_NTA_R1_R3_IMM9,
EM_LD2_C_NC_R1_R3_IMM9,
EM_LD2_C_NC_NT1_R1_R3_IMM9,
EM_LD2_C_NC_NTA_R1_R3_IMM9,
EM_LD4_C_NC_R1_R3_IMM9,
EM_LD4_C_NC_NT1_R1_R3_IMM9,
EM_LD4_C_NC_NTA_R1_R3_IMM9,
EM_LD8_C_NC_R1_R3_IMM9,
EM_LD8_C_NC_NT1_R1_R3_IMM9,
EM_LD8_C_NC_NTA_R1_R3_IMM9,
EM_LD1_C_CLR_ACQ_R1_R3_IMM9,
EM_LD1_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD1_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_LD2_C_CLR_ACQ_R1_R3_IMM9,
EM_LD2_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD2_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_LD4_C_CLR_ACQ_R1_R3_IMM9,
EM_LD4_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD4_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_LD8_C_CLR_ACQ_R1_R3_IMM9,
EM_LD8_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD8_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_ST1_R3_R2,
EM_ST1_NTA_R3_R2,
EM_ST2_R3_R2,
EM_ST2_NTA_R3_R2,
EM_ST4_R3_R2,
EM_ST4_NTA_R3_R2,
EM_ST8_R3_R2,
EM_ST8_NTA_R3_R2,
EM_ST1_REL_R3_R2,
EM_ST1_REL_NTA_R3_R2,
EM_ST2_REL_R3_R2,
EM_ST2_REL_NTA_R3_R2,
EM_ST4_REL_R3_R2,
EM_ST4_REL_NTA_R3_R2,
EM_ST8_REL_R3_R2,
EM_ST8_REL_NTA_R3_R2,
EM_ST8_SPILL_R3_R2,
EM_ST8_SPILL_NTA_R3_R2,
EM_ST1_R3_R2_IMM9,
EM_ST1_NTA_R3_R2_IMM9,
EM_ST2_R3_R2_IMM9,
EM_ST2_NTA_R3_R2_IMM9,
EM_ST4_R3_R2_IMM9,
EM_ST4_NTA_R3_R2_IMM9,
EM_ST8_R3_R2_IMM9,
EM_ST8_NTA_R3_R2_IMM9,
EM_ST1_REL_R3_R2_IMM9,
EM_ST1_REL_NTA_R3_R2_IMM9,
EM_ST2_REL_R3_R2_IMM9,
EM_ST2_REL_NTA_R3_R2_IMM9,
EM_ST4_REL_R3_R2_IMM9,
EM_ST4_REL_NTA_R3_R2_IMM9,
EM_ST8_REL_R3_R2_IMM9,
EM_ST8_REL_NTA_R3_R2_IMM9,
EM_ST8_SPILL_R3_R2_IMM9,
EM_ST8_SPILL_NTA_R3_R2_IMM9,
EM_LDFS_F1_R3,
EM_LDFS_NT1_F1_R3,
EM_LDFS_NTA_F1_R3,
EM_LDFD_F1_R3,
EM_LDFD_NT1_F1_R3,
EM_LDFD_NTA_F1_R3,
EM_LDF8_F1_R3,
EM_LDF8_NT1_F1_R3,
EM_LDF8_NTA_F1_R3,
EM_LDFE_F1_R3,
EM_LDFE_NT1_F1_R3,
EM_LDFE_NTA_F1_R3,
EM_LDFS_S_F1_R3,
EM_LDFS_S_NT1_F1_R3,
EM_LDFS_S_NTA_F1_R3,
EM_LDFD_S_F1_R3,
EM_LDFD_S_NT1_F1_R3,
EM_LDFD_S_NTA_F1_R3,
EM_LDF8_S_F1_R3,
EM_LDF8_S_NT1_F1_R3,
EM_LDF8_S_NTA_F1_R3,
EM_LDFE_S_F1_R3,
EM_LDFE_S_NT1_F1_R3,
EM_LDFE_S_NTA_F1_R3,
EM_LDFS_A_F1_R3,
EM_LDFS_A_NT1_F1_R3,
EM_LDFS_A_NTA_F1_R3,
EM_LDFD_A_F1_R3,
EM_LDFD_A_NT1_F1_R3,
EM_LDFD_A_NTA_F1_R3,
EM_LDF8_A_F1_R3,
EM_LDF8_A_NT1_F1_R3,
EM_LDF8_A_NTA_F1_R3,
EM_LDFE_A_F1_R3,
EM_LDFE_A_NT1_F1_R3,
EM_LDFE_A_NTA_F1_R3,
EM_LDFS_SA_F1_R3,
EM_LDFS_SA_NT1_F1_R3,
EM_LDFS_SA_NTA_F1_R3,
EM_LDFD_SA_F1_R3,
EM_LDFD_SA_NT1_F1_R3,
EM_LDFD_SA_NTA_F1_R3,
EM_LDF8_SA_F1_R3,
EM_LDF8_SA_NT1_F1_R3,
EM_LDF8_SA_NTA_F1_R3,
EM_LDFE_SA_F1_R3,
EM_LDFE_SA_NT1_F1_R3,
EM_LDFE_SA_NTA_F1_R3,
EM_LDF_FILL_F1_R3,
EM_LDF_FILL_NT1_F1_R3,
EM_LDF_FILL_NTA_F1_R3,
EM_LDFS_C_CLR_F1_R3,
EM_LDFS_C_CLR_NT1_F1_R3,
EM_LDFS_C_CLR_NTA_F1_R3,
EM_LDFD_C_CLR_F1_R3,
EM_LDFD_C_CLR_NT1_F1_R3,
EM_LDFD_C_CLR_NTA_F1_R3,
EM_LDF8_C_CLR_F1_R3,
EM_LDF8_C_CLR_NT1_F1_R3,
EM_LDF8_C_CLR_NTA_F1_R3,
EM_LDFE_C_CLR_F1_R3,
EM_LDFE_C_CLR_NT1_F1_R3,
EM_LDFE_C_CLR_NTA_F1_R3,
EM_LDFS_C_NC_F1_R3,
EM_LDFS_C_NC_NT1_F1_R3,
EM_LDFS_C_NC_NTA_F1_R3,
EM_LDFD_C_NC_F1_R3,
EM_LDFD_C_NC_NT1_F1_R3,
EM_LDFD_C_NC_NTA_F1_R3,
EM_LDF8_C_NC_F1_R3,
EM_LDF8_C_NC_NT1_F1_R3,
EM_LDF8_C_NC_NTA_F1_R3,
EM_LDFE_C_NC_F1_R3,
EM_LDFE_C_NC_NT1_F1_R3,
EM_LDFE_C_NC_NTA_F1_R3,
EM_LDFS_F1_R3_R2,
EM_LDFS_NT1_F1_R3_R2,
EM_LDFS_NTA_F1_R3_R2,
EM_LDFD_F1_R3_R2,
EM_LDFD_NT1_F1_R3_R2,
EM_LDFD_NTA_F1_R3_R2,
EM_LDF8_F1_R3_R2,
EM_LDF8_NT1_F1_R3_R2,
EM_LDF8_NTA_F1_R3_R2,
EM_LDFE_F1_R3_R2,
EM_LDFE_NT1_F1_R3_R2,
EM_LDFE_NTA_F1_R3_R2,
EM_LDFS_S_F1_R3_R2,
EM_LDFS_S_NT1_F1_R3_R2,
EM_LDFS_S_NTA_F1_R3_R2,
EM_LDFD_S_F1_R3_R2,
EM_LDFD_S_NT1_F1_R3_R2,
EM_LDFD_S_NTA_F1_R3_R2,
EM_LDF8_S_F1_R3_R2,
EM_LDF8_S_NT1_F1_R3_R2,
EM_LDF8_S_NTA_F1_R3_R2,
EM_LDFE_S_F1_R3_R2,
EM_LDFE_S_NT1_F1_R3_R2,
EM_LDFE_S_NTA_F1_R3_R2,
EM_LDFS_A_F1_R3_R2,
EM_LDFS_A_NT1_F1_R3_R2,
EM_LDFS_A_NTA_F1_R3_R2,
EM_LDFD_A_F1_R3_R2,
EM_LDFD_A_NT1_F1_R3_R2,
EM_LDFD_A_NTA_F1_R3_R2,
EM_LDF8_A_F1_R3_R2,
EM_LDF8_A_NT1_F1_R3_R2,
EM_LDF8_A_NTA_F1_R3_R2,
EM_LDFE_A_F1_R3_R2,
EM_LDFE_A_NT1_F1_R3_R2,
EM_LDFE_A_NTA_F1_R3_R2,
EM_LDFS_SA_F1_R3_R2,
EM_LDFS_SA_NT1_F1_R3_R2,
EM_LDFS_SA_NTA_F1_R3_R2,
EM_LDFD_SA_F1_R3_R2,
EM_LDFD_SA_NT1_F1_R3_R2,
EM_LDFD_SA_NTA_F1_R3_R2,
EM_LDF8_SA_F1_R3_R2,
EM_LDF8_SA_NT1_F1_R3_R2,
EM_LDF8_SA_NTA_F1_R3_R2,
EM_LDFE_SA_F1_R3_R2,
EM_LDFE_SA_NT1_F1_R3_R2,
EM_LDFE_SA_NTA_F1_R3_R2,
EM_LDF_FILL_F1_R3_R2,
EM_LDF_FILL_NT1_F1_R3_R2,
EM_LDF_FILL_NTA_F1_R3_R2,
EM_LDFS_C_CLR_F1_R3_R2,
EM_LDFS_C_CLR_NT1_F1_R3_R2,
EM_LDFS_C_CLR_NTA_F1_R3_R2,
EM_LDFD_C_CLR_F1_R3_R2,
EM_LDFD_C_CLR_NT1_F1_R3_R2,
EM_LDFD_C_CLR_NTA_F1_R3_R2,
EM_LDF8_C_CLR_F1_R3_R2,
EM_LDF8_C_CLR_NT1_F1_R3_R2,
EM_LDF8_C_CLR_NTA_F1_R3_R2,
EM_LDFE_C_CLR_F1_R3_R2,
EM_LDFE_C_CLR_NT1_F1_R3_R2,
EM_LDFE_C_CLR_NTA_F1_R3_R2,
EM_LDFS_C_NC_F1_R3_R2,
EM_LDFS_C_NC_NT1_F1_R3_R2,
EM_LDFS_C_NC_NTA_F1_R3_R2,
EM_LDFD_C_NC_F1_R3_R2,
EM_LDFD_C_NC_NT1_F1_R3_R2,
EM_LDFD_C_NC_NTA_F1_R3_R2,
EM_LDF8_C_NC_F1_R3_R2,
EM_LDF8_C_NC_NT1_F1_R3_R2,
EM_LDF8_C_NC_NTA_F1_R3_R2,
EM_LDFE_C_NC_F1_R3_R2,
EM_LDFE_C_NC_NT1_F1_R3_R2,
EM_LDFE_C_NC_NTA_F1_R3_R2,
EM_LDFS_F1_R3_IMM9,
EM_LDFS_NT1_F1_R3_IMM9,
EM_LDFS_NTA_F1_R3_IMM9,
EM_LDFD_F1_R3_IMM9,
EM_LDFD_NT1_F1_R3_IMM9,
EM_LDFD_NTA_F1_R3_IMM9,
EM_LDF8_F1_R3_IMM9,
EM_LDF8_NT1_F1_R3_IMM9,
EM_LDF8_NTA_F1_R3_IMM9,
EM_LDFE_F1_R3_IMM9,
EM_LDFE_NT1_F1_R3_IMM9,
EM_LDFE_NTA_F1_R3_IMM9,
EM_LDFS_S_F1_R3_IMM9,
EM_LDFS_S_NT1_F1_R3_IMM9,
EM_LDFS_S_NTA_F1_R3_IMM9,
EM_LDFD_S_F1_R3_IMM9,
EM_LDFD_S_NT1_F1_R3_IMM9,
EM_LDFD_S_NTA_F1_R3_IMM9,
EM_LDF8_S_F1_R3_IMM9,
EM_LDF8_S_NT1_F1_R3_IMM9,
EM_LDF8_S_NTA_F1_R3_IMM9,
EM_LDFE_S_F1_R3_IMM9,
EM_LDFE_S_NT1_F1_R3_IMM9,
EM_LDFE_S_NTA_F1_R3_IMM9,
EM_LDFS_A_F1_R3_IMM9,
EM_LDFS_A_NT1_F1_R3_IMM9,
EM_LDFS_A_NTA_F1_R3_IMM9,
EM_LDFD_A_F1_R3_IMM9,
EM_LDFD_A_NT1_F1_R3_IMM9,
EM_LDFD_A_NTA_F1_R3_IMM9,
EM_LDF8_A_F1_R3_IMM9,
EM_LDF8_A_NT1_F1_R3_IMM9,
EM_LDF8_A_NTA_F1_R3_IMM9,
EM_LDFE_A_F1_R3_IMM9,
EM_LDFE_A_NT1_F1_R3_IMM9,
EM_LDFE_A_NTA_F1_R3_IMM9,
EM_LDFS_SA_F1_R3_IMM9,
EM_LDFS_SA_NT1_F1_R3_IMM9,
EM_LDFS_SA_NTA_F1_R3_IMM9,
EM_LDFD_SA_F1_R3_IMM9,
EM_LDFD_SA_NT1_F1_R3_IMM9,
EM_LDFD_SA_NTA_F1_R3_IMM9,
EM_LDF8_SA_F1_R3_IMM9,
EM_LDF8_SA_NT1_F1_R3_IMM9,
EM_LDF8_SA_NTA_F1_R3_IMM9,
EM_LDFE_SA_F1_R3_IMM9,
EM_LDFE_SA_NT1_F1_R3_IMM9,
EM_LDFE_SA_NTA_F1_R3_IMM9,
EM_LDF_FILL_F1_R3_IMM9,
EM_LDF_FILL_NT1_F1_R3_IMM9,
EM_LDF_FILL_NTA_F1_R3_IMM9,
EM_LDFS_C_CLR_F1_R3_IMM9,
EM_LDFS_C_CLR_NT1_F1_R3_IMM9,
EM_LDFS_C_CLR_NTA_F1_R3_IMM9,
EM_LDFD_C_CLR_F1_R3_IMM9,
EM_LDFD_C_CLR_NT1_F1_R3_IMM9,
EM_LDFD_C_CLR_NTA_F1_R3_IMM9,
EM_LDF8_C_CLR_F1_R3_IMM9,
EM_LDF8_C_CLR_NT1_F1_R3_IMM9,
EM_LDF8_C_CLR_NTA_F1_R3_IMM9,
EM_LDFE_C_CLR_F1_R3_IMM9,
EM_LDFE_C_CLR_NT1_F1_R3_IMM9,
EM_LDFE_C_CLR_NTA_F1_R3_IMM9,
EM_LDFS_C_NC_F1_R3_IMM9,
EM_LDFS_C_NC_NT1_F1_R3_IMM9,
EM_LDFS_C_NC_NTA_F1_R3_IMM9,
EM_LDFD_C_NC_F1_R3_IMM9,
EM_LDFD_C_NC_NT1_F1_R3_IMM9,
EM_LDFD_C_NC_NTA_F1_R3_IMM9,
EM_LDF8_C_NC_F1_R3_IMM9,
EM_LDF8_C_NC_NT1_F1_R3_IMM9,
EM_LDF8_C_NC_NTA_F1_R3_IMM9,
EM_LDFE_C_NC_F1_R3_IMM9,
EM_LDFE_C_NC_NT1_F1_R3_IMM9,
EM_LDFE_C_NC_NTA_F1_R3_IMM9,
EM_STFS_R3_F2,
EM_STFS_NTA_R3_F2,
EM_STFD_R3_F2,
EM_STFD_NTA_R3_F2,
EM_STF8_R3_F2,
EM_STF8_NTA_R3_F2,
EM_STFE_R3_F2,
EM_STFE_NTA_R3_F2,
EM_STF_SPILL_R3_F2,
EM_STF_SPILL_NTA_R3_F2,
EM_STFS_R3_F2_IMM9,
EM_STFS_NTA_R3_F2_IMM9,
EM_STFD_R3_F2_IMM9,
EM_STFD_NTA_R3_F2_IMM9,
EM_STF8_R3_F2_IMM9,
EM_STF8_NTA_R3_F2_IMM9,
EM_STFE_R3_F2_IMM9,
EM_STFE_NTA_R3_F2_IMM9,
EM_STF_SPILL_R3_F2_IMM9,
EM_STF_SPILL_NTA_R3_F2_IMM9,
EM_LDFPS_F1_F2_R3,
EM_LDFPS_NT1_F1_F2_R3,
EM_LDFPS_NTA_F1_F2_R3,
EM_LDFPD_F1_F2_R3,
EM_LDFPD_NT1_F1_F2_R3,
EM_LDFPD_NTA_F1_F2_R3,
EM_LDFP8_F1_F2_R3,
EM_LDFP8_NT1_F1_F2_R3,
EM_LDFP8_NTA_F1_F2_R3,
EM_LDFPS_S_F1_F2_R3,
EM_LDFPS_S_NT1_F1_F2_R3,
EM_LDFPS_S_NTA_F1_F2_R3,
EM_LDFPD_S_F1_F2_R3,
EM_LDFPD_S_NT1_F1_F2_R3,
EM_LDFPD_S_NTA_F1_F2_R3,
EM_LDFP8_S_F1_F2_R3,
EM_LDFP8_S_NT1_F1_F2_R3,
EM_LDFP8_S_NTA_F1_F2_R3,
EM_LDFPS_A_F1_F2_R3,
EM_LDFPS_A_NT1_F1_F2_R3,
EM_LDFPS_A_NTA_F1_F2_R3,
EM_LDFPD_A_F1_F2_R3,
EM_LDFPD_A_NT1_F1_F2_R3,
EM_LDFPD_A_NTA_F1_F2_R3,
EM_LDFP8_A_F1_F2_R3,
EM_LDFP8_A_NT1_F1_F2_R3,
EM_LDFP8_A_NTA_F1_F2_R3,
EM_LDFPS_SA_F1_F2_R3,
EM_LDFPS_SA_NT1_F1_F2_R3,
EM_LDFPS_SA_NTA_F1_F2_R3,
EM_LDFPD_SA_F1_F2_R3,
EM_LDFPD_SA_NT1_F1_F2_R3,
EM_LDFPD_SA_NTA_F1_F2_R3,
EM_LDFP8_SA_F1_F2_R3,
EM_LDFP8_SA_NT1_F1_F2_R3,
EM_LDFP8_SA_NTA_F1_F2_R3,
EM_LDFPS_C_CLR_F1_F2_R3,
EM_LDFPS_C_CLR_NT1_F1_F2_R3,
EM_LDFPS_C_CLR_NTA_F1_F2_R3,
EM_LDFPD_C_CLR_F1_F2_R3,
EM_LDFPD_C_CLR_NT1_F1_F2_R3,
EM_LDFPD_C_CLR_NTA_F1_F2_R3,
EM_LDFP8_C_CLR_F1_F2_R3,
EM_LDFP8_C_CLR_NT1_F1_F2_R3,
EM_LDFP8_C_CLR_NTA_F1_F2_R3,
EM_LDFPS_C_NC_F1_F2_R3,
EM_LDFPS_C_NC_NT1_F1_F2_R3,
EM_LDFPS_C_NC_NTA_F1_F2_R3,
EM_LDFPD_C_NC_F1_F2_R3,
EM_LDFPD_C_NC_NT1_F1_F2_R3,
EM_LDFPD_C_NC_NTA_F1_F2_R3,
EM_LDFP8_C_NC_F1_F2_R3,
EM_LDFP8_C_NC_NT1_F1_F2_R3,
EM_LDFP8_C_NC_NTA_F1_F2_R3,
EM_LDFPS_F1_F2_R3_8,
EM_LDFPS_NT1_F1_F2_R3_8,
EM_LDFPS_NTA_F1_F2_R3_8,
EM_LDFPD_F1_F2_R3_16,
EM_LDFPD_NT1_F1_F2_R3_16,
EM_LDFPD_NTA_F1_F2_R3_16,
EM_LDFP8_F1_F2_R3_16,
EM_LDFP8_NT1_F1_F2_R3_16,
EM_LDFP8_NTA_F1_F2_R3_16,
EM_LDFPS_S_F1_F2_R3_8,
EM_LDFPS_S_NT1_F1_F2_R3_8,
EM_LDFPS_S_NTA_F1_F2_R3_8,
EM_LDFPD_S_F1_F2_R3_16,
EM_LDFPD_S_NT1_F1_F2_R3_16,
EM_LDFPD_S_NTA_F1_F2_R3_16,
EM_LDFP8_S_F1_F2_R3_16,
EM_LDFP8_S_NT1_F1_F2_R3_16,
EM_LDFP8_S_NTA_F1_F2_R3_16,
EM_LDFPS_A_F1_F2_R3_8,
EM_LDFPS_A_NT1_F1_F2_R3_8,
EM_LDFPS_A_NTA_F1_F2_R3_8,
EM_LDFPD_A_F1_F2_R3_16,
EM_LDFPD_A_NT1_F1_F2_R3_16,
EM_LDFPD_A_NTA_F1_F2_R3_16,
EM_LDFP8_A_F1_F2_R3_16,
EM_LDFP8_A_NT1_F1_F2_R3_16,
EM_LDFP8_A_NTA_F1_F2_R3_16,
EM_LDFPS_SA_F1_F2_R3_8,
EM_LDFPS_SA_NT1_F1_F2_R3_8,
EM_LDFPS_SA_NTA_F1_F2_R3_8,
EM_LDFPD_SA_F1_F2_R3_16,
EM_LDFPD_SA_NT1_F1_F2_R3_16,
EM_LDFPD_SA_NTA_F1_F2_R3_16,
EM_LDFP8_SA_F1_F2_R3_16,
EM_LDFP8_SA_NT1_F1_F2_R3_16,
EM_LDFP8_SA_NTA_F1_F2_R3_16,
EM_LDFPS_C_CLR_F1_F2_R3_8,
EM_LDFPS_C_CLR_NT1_F1_F2_R3_8,
EM_LDFPS_C_CLR_NTA_F1_F2_R3_8,
EM_LDFPD_C_CLR_F1_F2_R3_16,
EM_LDFPD_C_CLR_NT1_F1_F2_R3_16,
EM_LDFPD_C_CLR_NTA_F1_F2_R3_16,
EM_LDFP8_C_CLR_F1_F2_R3_16,
EM_LDFP8_C_CLR_NT1_F1_F2_R3_16,
EM_LDFP8_C_CLR_NTA_F1_F2_R3_16,
EM_LDFPS_C_NC_F1_F2_R3_8,
EM_LDFPS_C_NC_NT1_F1_F2_R3_8,
EM_LDFPS_C_NC_NTA_F1_F2_R3_8,
EM_LDFPD_C_NC_F1_F2_R3_16,
EM_LDFPD_C_NC_NT1_F1_F2_R3_16,
EM_LDFPD_C_NC_NTA_F1_F2_R3_16,
EM_LDFP8_C_NC_F1_F2_R3_16,
EM_LDFP8_C_NC_NT1_F1_F2_R3_16,
EM_LDFP8_C_NC_NTA_F1_F2_R3_16,
EM_LFETCH_R3,
EM_LFETCH_NT1_R3,
EM_LFETCH_NT2_R3,
EM_LFETCH_NTA_R3,
EM_LFETCH_EXCL_R3,
EM_LFETCH_EXCL_NT1_R3,
EM_LFETCH_EXCL_NT2_R3,
EM_LFETCH_EXCL_NTA_R3,
EM_LFETCH_FAULT_R3,
EM_LFETCH_FAULT_NT1_R3,
EM_LFETCH_FAULT_NT2_R3,
EM_LFETCH_FAULT_NTA_R3,
EM_LFETCH_FAULT_EXCL_R3,
EM_LFETCH_FAULT_EXCL_NT1_R3,
EM_LFETCH_FAULT_EXCL_NT2_R3,
EM_LFETCH_FAULT_EXCL_NTA_R3,
EM_LFETCH_R3_R2,
EM_LFETCH_NT1_R3_R2,
EM_LFETCH_NT2_R3_R2,
EM_LFETCH_NTA_R3_R2,
EM_LFETCH_EXCL_R3_R2,
EM_LFETCH_EXCL_NT1_R3_R2,
EM_LFETCH_EXCL_NT2_R3_R2,
EM_LFETCH_EXCL_NTA_R3_R2,
EM_LFETCH_FAULT_R3_R2,
EM_LFETCH_FAULT_NT1_R3_R2,
EM_LFETCH_FAULT_NT2_R3_R2,
EM_LFETCH_FAULT_NTA_R3_R2,
EM_LFETCH_FAULT_EXCL_R3_R2,
EM_LFETCH_FAULT_EXCL_NT1_R3_R2,
EM_LFETCH_FAULT_EXCL_NT2_R3_R2,
EM_LFETCH_FAULT_EXCL_NTA_R3_R2,
EM_LFETCH_R3_IMM9,
EM_LFETCH_NT1_R3_IMM9,
EM_LFETCH_NT2_R3_IMM9,
EM_LFETCH_NTA_R3_IMM9,
EM_LFETCH_EXCL_R3_IMM9,
EM_LFETCH_EXCL_NT1_R3_IMM9,
EM_LFETCH_EXCL_NT2_R3_IMM9,
EM_LFETCH_EXCL_NTA_R3_IMM9,
EM_LFETCH_FAULT_R3_IMM9,
EM_LFETCH_FAULT_NT1_R3_IMM9,
EM_LFETCH_FAULT_NT2_R3_IMM9,
EM_LFETCH_FAULT_NTA_R3_IMM9,
EM_LFETCH_FAULT_EXCL_R3_IMM9,
EM_LFETCH_FAULT_EXCL_NT1_R3_IMM9,
EM_LFETCH_FAULT_EXCL_NT2_R3_IMM9,
EM_LFETCH_FAULT_EXCL_NTA_R3_IMM9,
EM_CMPXCHG1_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_REL_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_REL_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_REL_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_REL_NTA_R1_R3_R2_AR_CCV,
EM_XCHG1_R1_R3_R2,
EM_XCHG1_NT1_R1_R3_R2,
EM_XCHG1_NTA_R1_R3_R2,
EM_XCHG2_R1_R3_R2,
EM_XCHG2_NT1_R1_R3_R2,
EM_XCHG2_NTA_R1_R3_R2,
EM_XCHG4_R1_R3_R2,
EM_XCHG4_NT1_R1_R3_R2,
EM_XCHG4_NTA_R1_R3_R2,
EM_XCHG8_R1_R3_R2,
EM_XCHG8_NT1_R1_R3_R2,
EM_XCHG8_NTA_R1_R3_R2,
EM_FETCHADD4_ACQ_R1_R3_INC3,
EM_FETCHADD4_ACQ_NT1_R1_R3_INC3,
EM_FETCHADD4_ACQ_NTA_R1_R3_INC3,
EM_FETCHADD8_ACQ_R1_R3_INC3,
EM_FETCHADD8_ACQ_NT1_R1_R3_INC3,
EM_FETCHADD8_ACQ_NTA_R1_R3_INC3,
EM_FETCHADD4_REL_R1_R3_INC3,
EM_FETCHADD4_REL_NT1_R1_R3_INC3,
EM_FETCHADD4_REL_NTA_R1_R3_INC3,
EM_FETCHADD8_REL_R1_R3_INC3,
EM_FETCHADD8_REL_NT1_R1_R3_INC3,
EM_FETCHADD8_REL_NTA_R1_R3_INC3,
EM_SETF_SIG_F1_R2,
EM_SETF_EXP_F1_R2,
EM_SETF_S_F1_R2,
EM_SETF_D_F1_R2,
EM_GETF_SIG_R1_F2,
EM_GETF_EXP_R1_F2,
EM_GETF_S_R1_F2,
EM_GETF_D_R1_F2,
EM_CHK_S_M_R2_TARGET25,
EM_CHK_S_F2_TARGET25,
EM_CHK_A_NC_R1_TARGET25,
EM_CHK_A_CLR_R1_TARGET25,
EM_CHK_A_NC_F1_TARGET25,
EM_CHK_A_CLR_F1_TARGET25,
EM_INVALA,
EM_FWB,
EM_MF,
EM_MF_A,
EM_SRLZ_D,
EM_SRLZ_I,
EM_SYNC_I,
EM_FLUSHRS,
EM_LOADRS,
EM_INVALA_E_R1,
EM_INVALA_E_F1,
EM_FC_R3,
EM_PTC_E_R3,
EM_MOV_M_AR3_R2,
EM_MOV_M_AR3_IMM8,
EM_MOV_M_R1_AR3,
EM_MOV_CR3_R2,
EM_MOV_R1_CR3,
EM_ALLOC_R1_AR_PFS_I_L_O_R,
EM_MOV_PSR_L_R2,
EM_MOV_PSR_UM_R2,
EM_MOV_R1_PSR,
EM_MOV_R1_PSR_UM,
EM_BREAK_M_IMM21,
EM_NOP_M_IMM21,
EM_PROBE_R_R1_R3_R2,
EM_PROBE_W_R1_R3_R2,
EM_PROBE_R_R1_R3_IMM2,
EM_PROBE_W_R1_R3_IMM2,
EM_PROBE_RW_FAULT_R3_IMM2,
EM_PROBE_R_FAULT_R3_IMM2,
EM_PROBE_W_FAULT_R3_IMM2,
EM_ITC_D_R2,
EM_ITC_I_R2,
EM_MOV_RR_R3_R2,
EM_MOV_DBR_R3_R2,
EM_MOV_IBR_R3_R2,
EM_MOV_PKR_R3_R2,
EM_MOV_PMC_R3_R2,
EM_MOV_PMD_R3_R2,
EM_MOV_MSR_R3_R2,
EM_ITR_D_DTR_R3_R2,
EM_ITR_I_ITR_R3_R2,
EM_MOV_R1_RR_R3,
EM_MOV_R1_DBR_R3,
EM_MOV_R1_IBR_R3,
EM_MOV_R1_PKR_R3,
EM_MOV_R1_PMC_R3,
EM_MOV_R1_MSR_R3,
EM_MOV_R1_PMD_R3,
EM_MOV_R1_CPUID_R3,
EM_SUM_IMM24,
EM_RUM_IMM24,
EM_SSM_IMM24,
EM_RSM_IMM24,
EM_PTC_L_R3_R2,
EM_PTC_G_R3_R2,
EM_PTC_GA_R3_R2,
EM_PTR_D_R3_R2,
EM_PTR_I_R3_R2,
EM_THASH_R1_R3,
EM_TTAG_R1_R3,
EM_TPA_R1_R3,
EM_TAK_R1_R3,
EM_HALT_R3,
EM_BR_COND_SPTK_FEW_TARGET25,
EM_BR_COND_SPTK_MANY_TARGET25,
EM_BR_COND_SPNT_FEW_TARGET25,
EM_BR_COND_SPNT_MANY_TARGET25,
EM_BR_COND_DPTK_FEW_TARGET25,
EM_BR_COND_DPTK_MANY_TARGET25,
EM_BR_COND_DPNT_FEW_TARGET25,
EM_BR_COND_DPNT_MANY_TARGET25,
EM_BR_COND_SPTK_FEW_CLR_TARGET25,
EM_BR_COND_SPTK_MANY_CLR_TARGET25,
EM_BR_COND_SPNT_FEW_CLR_TARGET25,
EM_BR_COND_SPNT_MANY_CLR_TARGET25,
EM_BR_COND_DPTK_FEW_CLR_TARGET25,
EM_BR_COND_DPTK_MANY_CLR_TARGET25,
EM_BR_COND_DPNT_FEW_CLR_TARGET25,
EM_BR_COND_DPNT_MANY_CLR_TARGET25,
EM_BR_WEXIT_SPTK_FEW_TARGET25,
EM_BR_WEXIT_SPTK_MANY_TARGET25,
EM_BR_WEXIT_SPNT_FEW_TARGET25,
EM_BR_WEXIT_SPNT_MANY_TARGET25,
EM_BR_WEXIT_DPTK_FEW_TARGET25,
EM_BR_WEXIT_DPTK_MANY_TARGET25,
EM_BR_WEXIT_DPNT_FEW_TARGET25,
EM_BR_WEXIT_DPNT_MANY_TARGET25,
EM_BR_WEXIT_SPTK_FEW_CLR_TARGET25,
EM_BR_WEXIT_SPTK_MANY_CLR_TARGET25,
EM_BR_WEXIT_SPNT_FEW_CLR_TARGET25,
EM_BR_WEXIT_SPNT_MANY_CLR_TARGET25,
EM_BR_WEXIT_DPTK_FEW_CLR_TARGET25,
EM_BR_WEXIT_DPTK_MANY_CLR_TARGET25,
EM_BR_WEXIT_DPNT_FEW_CLR_TARGET25,
EM_BR_WEXIT_DPNT_MANY_CLR_TARGET25,
EM_BR_WTOP_SPTK_FEW_TARGET25,
EM_BR_WTOP_SPTK_MANY_TARGET25,
EM_BR_WTOP_SPNT_FEW_TARGET25,
EM_BR_WTOP_SPNT_MANY_TARGET25,
EM_BR_WTOP_DPTK_FEW_TARGET25,
EM_BR_WTOP_DPTK_MANY_TARGET25,
EM_BR_WTOP_DPNT_FEW_TARGET25,
EM_BR_WTOP_DPNT_MANY_TARGET25,
EM_BR_WTOP_SPTK_FEW_CLR_TARGET25,
EM_BR_WTOP_SPTK_MANY_CLR_TARGET25,
EM_BR_WTOP_SPNT_FEW_CLR_TARGET25,
EM_BR_WTOP_SPNT_MANY_CLR_TARGET25,
EM_BR_WTOP_DPTK_FEW_CLR_TARGET25,
EM_BR_WTOP_DPTK_MANY_CLR_TARGET25,
EM_BR_WTOP_DPNT_FEW_CLR_TARGET25,
EM_BR_WTOP_DPNT_MANY_CLR_TARGET25,
EM_BR_CLOOP_SPTK_FEW_TARGET25,
EM_BR_CLOOP_SPTK_MANY_TARGET25,
EM_BR_CLOOP_SPNT_FEW_TARGET25,
EM_BR_CLOOP_SPNT_MANY_TARGET25,
EM_BR_CLOOP_DPTK_FEW_TARGET25,
EM_BR_CLOOP_DPTK_MANY_TARGET25,
EM_BR_CLOOP_DPNT_FEW_TARGET25,
EM_BR_CLOOP_DPNT_MANY_TARGET25,
EM_BR_CLOOP_SPTK_FEW_CLR_TARGET25,
EM_BR_CLOOP_SPTK_MANY_CLR_TARGET25,
EM_BR_CLOOP_SPNT_FEW_CLR_TARGET25,
EM_BR_CLOOP_SPNT_MANY_CLR_TARGET25,
EM_BR_CLOOP_DPTK_FEW_CLR_TARGET25,
EM_BR_CLOOP_DPTK_MANY_CLR_TARGET25,
EM_BR_CLOOP_DPNT_FEW_CLR_TARGET25,
EM_BR_CLOOP_DPNT_MANY_CLR_TARGET25,
EM_BR_CEXIT_SPTK_FEW_TARGET25,
EM_BR_CEXIT_SPTK_MANY_TARGET25,
EM_BR_CEXIT_SPNT_FEW_TARGET25,
EM_BR_CEXIT_SPNT_MANY_TARGET25,
EM_BR_CEXIT_DPTK_FEW_TARGET25,
EM_BR_CEXIT_DPTK_MANY_TARGET25,
EM_BR_CEXIT_DPNT_FEW_TARGET25,
EM_BR_CEXIT_DPNT_MANY_TARGET25,
EM_BR_CEXIT_SPTK_FEW_CLR_TARGET25,
EM_BR_CEXIT_SPTK_MANY_CLR_TARGET25,
EM_BR_CEXIT_SPNT_FEW_CLR_TARGET25,
EM_BR_CEXIT_SPNT_MANY_CLR_TARGET25,
EM_BR_CEXIT_DPTK_FEW_CLR_TARGET25,
EM_BR_CEXIT_DPTK_MANY_CLR_TARGET25,
EM_BR_CEXIT_DPNT_FEW_CLR_TARGET25,
EM_BR_CEXIT_DPNT_MANY_CLR_TARGET25,
EM_BR_CTOP_SPTK_FEW_TARGET25,
EM_BR_CTOP_SPTK_MANY_TARGET25,
EM_BR_CTOP_SPNT_FEW_TARGET25,
EM_BR_CTOP_SPNT_MANY_TARGET25,
EM_BR_CTOP_DPTK_FEW_TARGET25,
EM_BR_CTOP_DPTK_MANY_TARGET25,
EM_BR_CTOP_DPNT_FEW_TARGET25,
EM_BR_CTOP_DPNT_MANY_TARGET25,
EM_BR_CTOP_SPTK_FEW_CLR_TARGET25,
EM_BR_CTOP_SPTK_MANY_CLR_TARGET25,
EM_BR_CTOP_SPNT_FEW_CLR_TARGET25,
EM_BR_CTOP_SPNT_MANY_CLR_TARGET25,
EM_BR_CTOP_DPTK_FEW_CLR_TARGET25,
EM_BR_CTOP_DPTK_MANY_CLR_TARGET25,
EM_BR_CTOP_DPNT_FEW_CLR_TARGET25,
EM_BR_CTOP_DPNT_MANY_CLR_TARGET25,
EM_BR_CALL_SPTK_FEW_B1_TARGET25,
EM_BR_CALL_SPTK_MANY_B1_TARGET25,
EM_BR_CALL_SPNT_FEW_B1_TARGET25,
EM_BR_CALL_SPNT_MANY_B1_TARGET25,
EM_BR_CALL_DPTK_FEW_B1_TARGET25,
EM_BR_CALL_DPTK_MANY_B1_TARGET25,
EM_BR_CALL_DPNT_FEW_B1_TARGET25,
EM_BR_CALL_DPNT_MANY_B1_TARGET25,
EM_BR_CALL_SPTK_FEW_CLR_B1_TARGET25,
EM_BR_CALL_SPTK_MANY_CLR_B1_TARGET25,
EM_BR_CALL_SPNT_FEW_CLR_B1_TARGET25,
EM_BR_CALL_SPNT_MANY_CLR_B1_TARGET25,
EM_BR_CALL_DPTK_FEW_CLR_B1_TARGET25,
EM_BR_CALL_DPTK_MANY_CLR_B1_TARGET25,
EM_BR_CALL_DPNT_FEW_CLR_B1_TARGET25,
EM_BR_CALL_DPNT_MANY_CLR_B1_TARGET25,
EM_BR_COND_SPTK_FEW_B2,
EM_BR_COND_SPTK_MANY_B2,
EM_BR_COND_SPNT_FEW_B2,
EM_BR_COND_SPNT_MANY_B2,
EM_BR_COND_DPTK_FEW_B2,
EM_BR_COND_DPTK_MANY_B2,
EM_BR_COND_DPNT_FEW_B2,
EM_BR_COND_DPNT_MANY_B2,
EM_BR_COND_SPTK_FEW_CLR_B2,
EM_BR_COND_SPTK_MANY_CLR_B2,
EM_BR_COND_SPNT_FEW_CLR_B2,
EM_BR_COND_SPNT_MANY_CLR_B2,
EM_BR_COND_DPTK_FEW_CLR_B2,
EM_BR_COND_DPTK_MANY_CLR_B2,
EM_BR_COND_DPNT_FEW_CLR_B2,
EM_BR_COND_DPNT_MANY_CLR_B2,
EM_BR_IA_SPTK_FEW_B2,
EM_BR_IA_SPTK_MANY_B2,
EM_BR_IA_SPNT_FEW_B2,
EM_BR_IA_SPNT_MANY_B2,
EM_BR_IA_DPTK_FEW_B2,
EM_BR_IA_DPTK_MANY_B2,
EM_BR_IA_DPNT_FEW_B2,
EM_BR_IA_DPNT_MANY_B2,
EM_BR_IA_SPTK_FEW_CLR_B2,
EM_BR_IA_SPTK_MANY_CLR_B2,
EM_BR_IA_SPNT_FEW_CLR_B2,
EM_BR_IA_SPNT_MANY_CLR_B2,
EM_BR_IA_DPTK_FEW_CLR_B2,
EM_BR_IA_DPTK_MANY_CLR_B2,
EM_BR_IA_DPNT_FEW_CLR_B2,
EM_BR_IA_DPNT_MANY_CLR_B2,
EM_BR_RET_SPTK_FEW_B2,
EM_BR_RET_SPTK_MANY_B2,
EM_BR_RET_SPNT_FEW_B2,
EM_BR_RET_SPNT_MANY_B2,
EM_BR_RET_DPTK_FEW_B2,
EM_BR_RET_DPTK_MANY_B2,
EM_BR_RET_DPNT_FEW_B2,
EM_BR_RET_DPNT_MANY_B2,
EM_BR_RET_SPTK_FEW_CLR_B2,
EM_BR_RET_SPTK_MANY_CLR_B2,
EM_BR_RET_SPNT_FEW_CLR_B2,
EM_BR_RET_SPNT_MANY_CLR_B2,
EM_BR_RET_DPTK_FEW_CLR_B2,
EM_BR_RET_DPTK_MANY_CLR_B2,
EM_BR_RET_DPNT_FEW_CLR_B2,
EM_BR_RET_DPNT_MANY_CLR_B2,
EM_BR_CALL_SPTK_FEW_B1_B2,
EM_BR_CALL_SPTK_MANY_B1_B2,
EM_BR_CALL_SPNT_FEW_B1_B2,
EM_BR_CALL_SPNT_MANY_B1_B2,
EM_BR_CALL_DPTK_FEW_B1_B2,
EM_BR_CALL_DPTK_MANY_B1_B2,
EM_BR_CALL_DPNT_FEW_B1_B2,
EM_BR_CALL_DPNT_MANY_B1_B2,
EM_BR_CALL_SPTK_FEW_CLR_B1_B2,
EM_BR_CALL_SPTK_MANY_CLR_B1_B2,
EM_BR_CALL_SPNT_FEW_CLR_B1_B2,
EM_BR_CALL_SPNT_MANY_CLR_B1_B2,
EM_BR_CALL_DPTK_FEW_CLR_B1_B2,
EM_BR_CALL_DPTK_MANY_CLR_B1_B2,
EM_BR_CALL_DPNT_FEW_CLR_B1_B2,
EM_BR_CALL_DPNT_MANY_CLR_B1_B2,
EM_BRP_SPTK_TARGET25_TAG13,
EM_BRP_SPTK_IMP_TARGET25_TAG13,
EM_BRP_LOOP_TARGET25_TAG13,
EM_BRP_LOOP_IMP_TARGET25_TAG13,
EM_BRP_DPTK_TARGET25_TAG13,
EM_BRP_DPTK_IMP_TARGET25_TAG13,
EM_BRP_EXIT_TARGET25_TAG13,
EM_BRP_EXIT_IMP_TARGET25_TAG13,
EM_BRP_SPTK_B2_TAG13,
EM_BRP_SPTK_IMP_B2_TAG13,
EM_BRP_DPTK_B2_TAG13,
EM_BRP_DPTK_IMP_B2_TAG13,
EM_BRP_RET_SPTK_B2_TAG13,
EM_BRP_RET_SPTK_IMP_B2_TAG13,
EM_BRP_RET_DPTK_B2_TAG13,
EM_BRP_RET_DPTK_IMP_B2_TAG13,
EM_COVER,
EM_CLRRRB,
EM_CLRRRB_PR,
EM_RFI,
EM_RFI_X,
EM_BSW_0,
EM_BSW_1,
EM_EPC,
EM_BREAK_B_IMM21,
EM_NOP_B_IMM21,
EM_FMA_S0_F1_F3_F4_F2,
EM_FMA_S1_F1_F3_F4_F2,
EM_FMA_S2_F1_F3_F4_F2,
EM_FMA_S3_F1_F3_F4_F2,
EM_FMA_S_S0_F1_F3_F4_F2,
EM_FMA_S_S1_F1_F3_F4_F2,
EM_FMA_S_S2_F1_F3_F4_F2,
EM_FMA_S_S3_F1_F3_F4_F2,
EM_FMA_D_S0_F1_F3_F4_F2,
EM_FMA_D_S1_F1_F3_F4_F2,
EM_FMA_D_S2_F1_F3_F4_F2,
EM_FMA_D_S3_F1_F3_F4_F2,
EM_FPMA_S0_F1_F3_F4_F2,
EM_FPMA_S1_F1_F3_F4_F2,
EM_FPMA_S2_F1_F3_F4_F2,
EM_FPMA_S3_F1_F3_F4_F2,
EM_FMS_S0_F1_F3_F4_F2,
EM_FMS_S1_F1_F3_F4_F2,
EM_FMS_S2_F1_F3_F4_F2,
EM_FMS_S3_F1_F3_F4_F2,
EM_FMS_S_S0_F1_F3_F4_F2,
EM_FMS_S_S1_F1_F3_F4_F2,
EM_FMS_S_S2_F1_F3_F4_F2,
EM_FMS_S_S3_F1_F3_F4_F2,
EM_FMS_D_S0_F1_F3_F4_F2,
EM_FMS_D_S1_F1_F3_F4_F2,
EM_FMS_D_S2_F1_F3_F4_F2,
EM_FMS_D_S3_F1_F3_F4_F2,
EM_FPMS_S0_F1_F3_F4_F2,
EM_FPMS_S1_F1_F3_F4_F2,
EM_FPMS_S2_F1_F3_F4_F2,
EM_FPMS_S3_F1_F3_F4_F2,
EM_FNMA_S0_F1_F3_F4_F2,
EM_FNMA_S1_F1_F3_F4_F2,
EM_FNMA_S2_F1_F3_F4_F2,
EM_FNMA_S3_F1_F3_F4_F2,
EM_FNMA_S_S0_F1_F3_F4_F2,
EM_FNMA_S_S1_F1_F3_F4_F2,
EM_FNMA_S_S2_F1_F3_F4_F2,
EM_FNMA_S_S3_F1_F3_F4_F2,
EM_FNMA_D_S0_F1_F3_F4_F2,
EM_FNMA_D_S1_F1_F3_F4_F2,
EM_FNMA_D_S2_F1_F3_F4_F2,
EM_FNMA_D_S3_F1_F3_F4_F2,
EM_FPNMA_S0_F1_F3_F4_F2,
EM_FPNMA_S1_F1_F3_F4_F2,
EM_FPNMA_S2_F1_F3_F4_F2,
EM_FPNMA_S3_F1_F3_F4_F2,
EM_XMA_L_F1_F3_F4_F2,
EM_XMA_H_F1_F3_F4_F2,
EM_XMA_HU_F1_F3_F4_F2,
EM_FSELECT_F1_F3_F4_F2,
EM_FCMP_EQ_S0_P1_P2_F2_F3,
EM_FCMP_EQ_S1_P1_P2_F2_F3,
EM_FCMP_EQ_S2_P1_P2_F2_F3,
EM_FCMP_EQ_S3_P1_P2_F2_F3,
EM_FCMP_LT_S0_P1_P2_F2_F3,
EM_FCMP_LT_S1_P1_P2_F2_F3,
EM_FCMP_LT_S2_P1_P2_F2_F3,
EM_FCMP_LT_S3_P1_P2_F2_F3,
EM_FCMP_LE_S0_P1_P2_F2_F3,
EM_FCMP_LE_S1_P1_P2_F2_F3,
EM_FCMP_LE_S2_P1_P2_F2_F3,
EM_FCMP_LE_S3_P1_P2_F2_F3,
EM_FCMP_UNORD_S0_P1_P2_F2_F3,
EM_FCMP_UNORD_S1_P1_P2_F2_F3,
EM_FCMP_UNORD_S2_P1_P2_F2_F3,
EM_FCMP_UNORD_S3_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S0_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S1_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S2_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S3_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S0_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S1_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S2_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S3_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S0_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S1_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S2_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S3_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S0_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S1_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S2_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S3_P1_P2_F2_F3,
EM_FCLASS_M_P1_P2_F2_FCLASS9,
EM_FCLASS_M_UNC_P1_P2_F2_FCLASS9,
EM_FRCPA_S0_F1_P2_F2_F3,
EM_FRCPA_S1_F1_P2_F2_F3,
EM_FRCPA_S2_F1_P2_F2_F3,
EM_FRCPA_S3_F1_P2_F2_F3,
EM_FPRCPA_S0_F1_P2_F2_F3,
EM_FPRCPA_S1_F1_P2_F2_F3,
EM_FPRCPA_S2_F1_P2_F2_F3,
EM_FPRCPA_S3_F1_P2_F2_F3,
EM_FRSQRTA_S0_F1_P2_F3,
EM_FRSQRTA_S1_F1_P2_F3,
EM_FRSQRTA_S2_F1_P2_F3,
EM_FRSQRTA_S3_F1_P2_F3,
EM_FPRSQRTA_S0_F1_P2_F3,
EM_FPRSQRTA_S1_F1_P2_F3,
EM_FPRSQRTA_S2_F1_P2_F3,
EM_FPRSQRTA_S3_F1_P2_F3,
EM_FMIN_S0_F1_F2_F3,
EM_FMIN_S1_F1_F2_F3,
EM_FMIN_S2_F1_F2_F3,
EM_FMIN_S3_F1_F2_F3,
EM_FMAX_S0_F1_F2_F3,
EM_FMAX_S1_F1_F2_F3,
EM_FMAX_S2_F1_F2_F3,
EM_FMAX_S3_F1_F2_F3,
EM_FAMIN_S0_F1_F2_F3,
EM_FAMIN_S1_F1_F2_F3,
EM_FAMIN_S2_F1_F2_F3,
EM_FAMIN_S3_F1_F2_F3,
EM_FAMAX_S0_F1_F2_F3,
EM_FAMAX_S1_F1_F2_F3,
EM_FAMAX_S2_F1_F2_F3,
EM_FAMAX_S3_F1_F2_F3,
EM_FPMIN_S0_F1_F2_F3,
EM_FPMIN_S1_F1_F2_F3,
EM_FPMIN_S2_F1_F2_F3,
EM_FPMIN_S3_F1_F2_F3,
EM_FPMAX_S0_F1_F2_F3,
EM_FPMAX_S1_F1_F2_F3,
EM_FPMAX_S2_F1_F2_F3,
EM_FPMAX_S3_F1_F2_F3,
EM_FPAMIN_S0_F1_F2_F3,
EM_FPAMIN_S1_F1_F2_F3,
EM_FPAMIN_S2_F1_F2_F3,
EM_FPAMIN_S3_F1_F2_F3,
EM_FPAMAX_S0_F1_F2_F3,
EM_FPAMAX_S1_F1_F2_F3,
EM_FPAMAX_S2_F1_F2_F3,
EM_FPAMAX_S3_F1_F2_F3,
EM_FPCMP_EQ_S0_F1_F2_F3,
EM_FPCMP_EQ_S1_F1_F2_F3,
EM_FPCMP_EQ_S2_F1_F2_F3,
EM_FPCMP_EQ_S3_F1_F2_F3,
EM_FPCMP_LT_S0_F1_F2_F3,
EM_FPCMP_LT_S1_F1_F2_F3,
EM_FPCMP_LT_S2_F1_F2_F3,
EM_FPCMP_LT_S3_F1_F2_F3,
EM_FPCMP_LE_S0_F1_F2_F3,
EM_FPCMP_LE_S1_F1_F2_F3,
EM_FPCMP_LE_S2_F1_F2_F3,
EM_FPCMP_LE_S3_F1_F2_F3,
EM_FPCMP_UNORD_S0_F1_F2_F3,
EM_FPCMP_UNORD_S1_F1_F2_F3,
EM_FPCMP_UNORD_S2_F1_F2_F3,
EM_FPCMP_UNORD_S3_F1_F2_F3,
EM_FPCMP_NEQ_S0_F1_F2_F3,
EM_FPCMP_NEQ_S1_F1_F2_F3,
EM_FPCMP_NEQ_S2_F1_F2_F3,
EM_FPCMP_NEQ_S3_F1_F2_F3,
EM_FPCMP_NLT_S0_F1_F2_F3,
EM_FPCMP_NLT_S1_F1_F2_F3,
EM_FPCMP_NLT_S2_F1_F2_F3,
EM_FPCMP_NLT_S3_F1_F2_F3,
EM_FPCMP_NLE_S0_F1_F2_F3,
EM_FPCMP_NLE_S1_F1_F2_F3,
EM_FPCMP_NLE_S2_F1_F2_F3,
EM_FPCMP_NLE_S3_F1_F2_F3,
EM_FPCMP_ORD_S0_F1_F2_F3,
EM_FPCMP_ORD_S1_F1_F2_F3,
EM_FPCMP_ORD_S2_F1_F2_F3,
EM_FPCMP_ORD_S3_F1_F2_F3,
EM_FMERGE_S_F1_F2_F3,
EM_FMERGE_NS_F1_F2_F3,
EM_FMERGE_SE_F1_F2_F3,
EM_FMIX_LR_F1_F2_F3,
EM_FMIX_R_F1_F2_F3,
EM_FMIX_L_F1_F2_F3,
EM_FSXT_R_F1_F2_F3,
EM_FSXT_L_F1_F2_F3,
EM_FPACK_F1_F2_F3,
EM_FSWAP_F1_F2_F3,
EM_FSWAP_NL_F1_F2_F3,
EM_FSWAP_NR_F1_F2_F3,
EM_FAND_F1_F2_F3,
EM_FANDCM_F1_F2_F3,
EM_FOR_F1_F2_F3,
EM_FXOR_F1_F2_F3,
EM_FPMERGE_S_F1_F2_F3,
EM_FPMERGE_NS_F1_F2_F3,
EM_FPMERGE_SE_F1_F2_F3,
EM_FCVT_FX_S0_F1_F2,
EM_FCVT_FX_S1_F1_F2,
EM_FCVT_FX_S2_F1_F2,
EM_FCVT_FX_S3_F1_F2,
EM_FCVT_FXU_S0_F1_F2,
EM_FCVT_FXU_S1_F1_F2,
EM_FCVT_FXU_S2_F1_F2,
EM_FCVT_FXU_S3_F1_F2,
EM_FCVT_FX_TRUNC_S0_F1_F2,
EM_FCVT_FX_TRUNC_S1_F1_F2,
EM_FCVT_FX_TRUNC_S2_F1_F2,
EM_FCVT_FX_TRUNC_S3_F1_F2,
EM_FCVT_FXU_TRUNC_S0_F1_F2,
EM_FCVT_FXU_TRUNC_S1_F1_F2,
EM_FCVT_FXU_TRUNC_S2_F1_F2,
EM_FCVT_FXU_TRUNC_S3_F1_F2,
EM_FPCVT_FX_S0_F1_F2,
EM_FPCVT_FX_S1_F1_F2,
EM_FPCVT_FX_S2_F1_F2,
EM_FPCVT_FX_S3_F1_F2,
EM_FPCVT_FXU_S0_F1_F2,
EM_FPCVT_FXU_S1_F1_F2,
EM_FPCVT_FXU_S2_F1_F2,
EM_FPCVT_FXU_S3_F1_F2,
EM_FPCVT_FX_TRUNC_S0_F1_F2,
EM_FPCVT_FX_TRUNC_S1_F1_F2,
EM_FPCVT_FX_TRUNC_S2_F1_F2,
EM_FPCVT_FX_TRUNC_S3_F1_F2,
EM_FPCVT_FXU_TRUNC_S0_F1_F2,
EM_FPCVT_FXU_TRUNC_S1_F1_F2,
EM_FPCVT_FXU_TRUNC_S2_F1_F2,
EM_FPCVT_FXU_TRUNC_S3_F1_F2,
EM_FCVT_XF_F1_F2,
EM_FSETC_S0_AMASK7_OMASK7,
EM_FSETC_S1_AMASK7_OMASK7,
EM_FSETC_S2_AMASK7_OMASK7,
EM_FSETC_S3_AMASK7_OMASK7,
EM_FCLRF_S0,
EM_FCLRF_S1,
EM_FCLRF_S2,
EM_FCLRF_S3,
EM_FCHKF_S0_TARGET25,
EM_FCHKF_S1_TARGET25,
EM_FCHKF_S2_TARGET25,
EM_FCHKF_S3_TARGET25,
EM_BREAK_F_IMM21,
EM_NOP_F_IMM21,
EM_BREAK_X_IMM62,
EM_NOP_X_IMM62,
EM_MOVL_R1_IMM64,
EM_BRL_COND_SPTK_FEW_TARGET64,
EM_BRL_COND_SPTK_MANY_TARGET64,
EM_BRL_COND_SPNT_FEW_TARGET64,
EM_BRL_COND_SPNT_MANY_TARGET64,
EM_BRL_COND_DPTK_FEW_TARGET64,
EM_BRL_COND_DPTK_MANY_TARGET64,
EM_BRL_COND_DPNT_FEW_TARGET64,
EM_BRL_COND_DPNT_MANY_TARGET64,
EM_BRL_COND_SPTK_FEW_CLR_TARGET64,
EM_BRL_COND_SPTK_MANY_CLR_TARGET64,
EM_BRL_COND_SPNT_FEW_CLR_TARGET64,
EM_BRL_COND_SPNT_MANY_CLR_TARGET64,
EM_BRL_COND_DPTK_FEW_CLR_TARGET64,
EM_BRL_COND_DPTK_MANY_CLR_TARGET64,
EM_BRL_COND_DPNT_FEW_CLR_TARGET64,
EM_BRL_COND_DPNT_MANY_CLR_TARGET64,
EM_BRL_CALL_SPTK_FEW_B1_TARGET64,
EM_BRL_CALL_SPTK_MANY_B1_TARGET64,
EM_BRL_CALL_SPNT_FEW_B1_TARGET64,
EM_BRL_CALL_SPNT_MANY_B1_TARGET64,
EM_BRL_CALL_DPTK_FEW_B1_TARGET64,
EM_BRL_CALL_DPTK_MANY_B1_TARGET64,
EM_BRL_CALL_DPNT_FEW_B1_TARGET64,
EM_BRL_CALL_DPNT_MANY_B1_TARGET64,
EM_BRL_CALL_SPTK_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_SPTK_MANY_CLR_B1_TARGET64,
EM_BRL_CALL_SPNT_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_SPNT_MANY_CLR_B1_TARGET64,
EM_BRL_CALL_DPTK_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_DPTK_MANY_CLR_B1_TARGET64,
EM_BRL_CALL_DPNT_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_DPNT_MANY_CLR_B1_TARGET64,
EM_INST_LAST
} Inst_id_t;

#else /* C++ code */

typedef unsigned Inst_id_t;

typedef enum Inst_id_e
{
EM_INST_NONE = 0,
EM_ILLOP = EM_INST_NONE,
EM_IGNOP,
EM_ADD_R1_R2_R3,
EM_ADD_R1_R2_R3_1,
EM_SUB_R1_R2_R3,
EM_SUB_R1_R2_R3_1,
EM_ADDP4_R1_R2_R3,
EM_AND_R1_R2_R3,
EM_ANDCM_R1_R2_R3,
EM_OR_R1_R2_R3,
EM_XOR_R1_R2_R3,
EM_SHLADD_R1_R2_COUNT2_R3,
EM_SHLADDP4_R1_R2_COUNT2_R3,
EM_SUB_R1_IMM8_R3,
EM_AND_R1_IMM8_R3,
EM_ANDCM_R1_IMM8_R3,
EM_OR_R1_IMM8_R3,
EM_XOR_R1_IMM8_R3,
EM_ADDS_R1_IMM14_R3,
EM_ADDP4_R1_IMM14_R3,
EM_ADDL_R1_IMM22_R3,
EM_CMP_LT_P1_P2_R2_R3,
EM_CMP_LTU_P1_P2_R2_R3,
EM_CMP_EQ_P1_P2_R2_R3,
EM_CMP_LT_UNC_P1_P2_R2_R3,
EM_CMP_LTU_UNC_P1_P2_R2_R3,
EM_CMP_EQ_UNC_P1_P2_R2_R3,
EM_CMP_EQ_AND_P1_P2_R2_R3,
EM_CMP_EQ_OR_P1_P2_R2_R3,
EM_CMP_EQ_OR_ANDCM_P1_P2_R2_R3,
EM_CMP_NE_AND_P1_P2_R2_R3,
EM_CMP_NE_OR_P1_P2_R2_R3,
EM_CMP_NE_OR_ANDCM_P1_P2_R2_R3,
EM_CMP4_LT_P1_P2_R2_R3,
EM_CMP4_LTU_P1_P2_R2_R3,
EM_CMP4_EQ_P1_P2_R2_R3,
EM_CMP4_LT_UNC_P1_P2_R2_R3,
EM_CMP4_LTU_UNC_P1_P2_R2_R3,
EM_CMP4_EQ_UNC_P1_P2_R2_R3,
EM_CMP4_EQ_AND_P1_P2_R2_R3,
EM_CMP4_EQ_OR_P1_P2_R2_R3,
EM_CMP4_EQ_OR_ANDCM_P1_P2_R2_R3,
EM_CMP4_NE_AND_P1_P2_R2_R3,
EM_CMP4_NE_OR_P1_P2_R2_R3,
EM_CMP4_NE_OR_ANDCM_P1_P2_R2_R3,
EM_CMP_GT_AND_P1_P2_R0_R3,
EM_CMP_GT_OR_P1_P2_R0_R3,
EM_CMP_GT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_LE_AND_P1_P2_R0_R3,
EM_CMP_LE_OR_P1_P2_R0_R3,
EM_CMP_LE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_GE_AND_P1_P2_R0_R3,
EM_CMP_GE_OR_P1_P2_R0_R3,
EM_CMP_GE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_LT_AND_P1_P2_R0_R3,
EM_CMP_LT_OR_P1_P2_R0_R3,
EM_CMP_LT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_GT_AND_P1_P2_R0_R3,
EM_CMP4_GT_OR_P1_P2_R0_R3,
EM_CMP4_GT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_LE_AND_P1_P2_R0_R3,
EM_CMP4_LE_OR_P1_P2_R0_R3,
EM_CMP4_LE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_GE_AND_P1_P2_R0_R3,
EM_CMP4_GE_OR_P1_P2_R0_R3,
EM_CMP4_GE_OR_ANDCM_P1_P2_R0_R3,
EM_CMP4_LT_AND_P1_P2_R0_R3,
EM_CMP4_LT_OR_P1_P2_R0_R3,
EM_CMP4_LT_OR_ANDCM_P1_P2_R0_R3,
EM_CMP_LT_P1_P2_IMM8_R3,
EM_CMP_LTU_P1_P2_IMM8_R3,
EM_CMP_EQ_P1_P2_IMM8_R3,
EM_CMP_LT_UNC_P1_P2_IMM8_R3,
EM_CMP_LTU_UNC_P1_P2_IMM8_R3,
EM_CMP_EQ_UNC_P1_P2_IMM8_R3,
EM_CMP_EQ_AND_P1_P2_IMM8_R3,
EM_CMP_EQ_OR_P1_P2_IMM8_R3,
EM_CMP_EQ_OR_ANDCM_P1_P2_IMM8_R3,
EM_CMP_NE_AND_P1_P2_IMM8_R3,
EM_CMP_NE_OR_P1_P2_IMM8_R3,
EM_CMP_NE_OR_ANDCM_P1_P2_IMM8_R3,
EM_CMP4_LT_P1_P2_IMM8_R3,
EM_CMP4_LTU_P1_P2_IMM8_R3,
EM_CMP4_EQ_P1_P2_IMM8_R3,
EM_CMP4_LT_UNC_P1_P2_IMM8_R3,
EM_CMP4_LTU_UNC_P1_P2_IMM8_R3,
EM_CMP4_EQ_UNC_P1_P2_IMM8_R3,
EM_CMP4_EQ_AND_P1_P2_IMM8_R3,
EM_CMP4_EQ_OR_P1_P2_IMM8_R3,
EM_CMP4_EQ_OR_ANDCM_P1_P2_IMM8_R3,
EM_CMP4_NE_AND_P1_P2_IMM8_R3,
EM_CMP4_NE_OR_P1_P2_IMM8_R3,
EM_CMP4_NE_OR_ANDCM_P1_P2_IMM8_R3,
EM_PADD1_R1_R2_R3,
EM_PADD2_R1_R2_R3,
EM_PADD4_R1_R2_R3,
EM_PADD1_SSS_R1_R2_R3,
EM_PADD2_SSS_R1_R2_R3,
EM_PADD1_UUU_R1_R2_R3,
EM_PADD2_UUU_R1_R2_R3,
EM_PADD1_UUS_R1_R2_R3,
EM_PADD2_UUS_R1_R2_R3,
EM_PSUB1_R1_R2_R3,
EM_PSUB2_R1_R2_R3,
EM_PSUB4_R1_R2_R3,
EM_PSUB1_SSS_R1_R2_R3,
EM_PSUB2_SSS_R1_R2_R3,
EM_PSUB1_UUU_R1_R2_R3,
EM_PSUB2_UUU_R1_R2_R3,
EM_PSUB1_UUS_R1_R2_R3,
EM_PSUB2_UUS_R1_R2_R3,
EM_PAVG1_R1_R2_R3,
EM_PAVG2_R1_R2_R3,
EM_PAVG1_RAZ_R1_R2_R3,
EM_PAVG2_RAZ_R1_R2_R3,
EM_PAVGSUB1_R1_R2_R3,
EM_PAVGSUB2_R1_R2_R3,
EM_PCMP1_EQ_R1_R2_R3,
EM_PCMP2_EQ_R1_R2_R3,
EM_PCMP4_EQ_R1_R2_R3,
EM_PCMP1_GT_R1_R2_R3,
EM_PCMP2_GT_R1_R2_R3,
EM_PCMP4_GT_R1_R2_R3,
EM_PSHLADD2_R1_R2_COUNT2_R3,
EM_PSHRADD2_R1_R2_COUNT2_R3,
EM_PMPYSHR2_R1_R2_R3_COUNT2,
EM_PMPYSHR2_U_R1_R2_R3_COUNT2,
EM_PMPY2_R_R1_R2_R3,
EM_PMPY2_L_R1_R2_R3,
EM_MIX1_R_R1_R2_R3,
EM_MIX2_R_R1_R2_R3,
EM_MIX4_R_R1_R2_R3,
EM_MIX1_L_R1_R2_R3,
EM_MIX2_L_R1_R2_R3,
EM_MIX4_L_R1_R2_R3,
EM_PACK2_USS_R1_R2_R3,
EM_PACK2_SSS_R1_R2_R3,
EM_PACK4_SSS_R1_R2_R3,
EM_UNPACK1_H_R1_R2_R3,
EM_UNPACK2_H_R1_R2_R3,
EM_UNPACK4_H_R1_R2_R3,
EM_UNPACK1_L_R1_R2_R3,
EM_UNPACK2_L_R1_R2_R3,
EM_UNPACK4_L_R1_R2_R3,
EM_PMIN1_U_R1_R2_R3,
EM_PMAX1_U_R1_R2_R3,
EM_PMIN2_R1_R2_R3,
EM_PMAX2_R1_R2_R3,
EM_PSAD1_R1_R2_R3,
EM_MUX1_R1_R2_MBTYPE4,
EM_MUX2_R1_R2_MHTYPE8,
EM_PSHR2_R1_R3_R2,
EM_PSHR4_R1_R3_R2,
EM_SHR_R1_R3_R2,
EM_PSHR2_U_R1_R3_R2,
EM_PSHR4_U_R1_R3_R2,
EM_SHR_U_R1_R3_R2,
EM_PSHR2_R1_R3_COUNT5,
EM_PSHR4_R1_R3_COUNT5,
EM_PSHR2_U_R1_R3_COUNT5,
EM_PSHR4_U_R1_R3_COUNT5,
EM_PSHL2_R1_R2_R3,
EM_PSHL4_R1_R2_R3,
EM_SHL_R1_R2_R3,
EM_PSHL2_R1_R2_COUNT5,
EM_PSHL4_R1_R2_COUNT5,
EM_POPCNT_R1_R3,
EM_SHRP_R1_R2_R3_COUNT6,
EM_EXTR_U_R1_R3_POS6_LEN6,
EM_EXTR_R1_R3_POS6_LEN6,
EM_DEP_Z_R1_R2_POS6_LEN6,
EM_DEP_Z_R1_IMM8_POS6_LEN6,
EM_DEP_R1_IMM1_R3_POS6_LEN6,
EM_DEP_R1_R2_R3_POS6_LEN4,
EM_TBIT_Z_P1_P2_R3_POS6,
EM_TBIT_Z_UNC_P1_P2_R3_POS6,
EM_TBIT_Z_AND_P1_P2_R3_POS6,
EM_TBIT_NZ_AND_P1_P2_R3_POS6,
EM_TBIT_Z_OR_P1_P2_R3_POS6,
EM_TBIT_NZ_OR_P1_P2_R3_POS6,
EM_TBIT_Z_OR_ANDCM_P1_P2_R3_POS6,
EM_TBIT_NZ_OR_ANDCM_P1_P2_R3_POS6,
EM_TNAT_Z_P1_P2_R3,
EM_TNAT_Z_UNC_P1_P2_R3,
EM_TNAT_Z_AND_P1_P2_R3,
EM_TNAT_NZ_AND_P1_P2_R3,
EM_TNAT_Z_OR_P1_P2_R3,
EM_TNAT_NZ_OR_P1_P2_R3,
EM_TNAT_Z_OR_ANDCM_P1_P2_R3,
EM_TNAT_NZ_OR_ANDCM_P1_P2_R3,
EM_BREAK_I_IMM21,
EM_NOP_I_IMM21,
EM_CHK_S_I_R2_TARGET25,
EM_MOV_SPTK_B1_R2_TAG13,
EM_MOV_SPTK_IMP_B1_R2_TAG13,
EM_MOV_B1_R2_TAG13,
EM_MOV_IMP_B1_R2_TAG13,
EM_MOV_DPTK_B1_R2_TAG13,
EM_MOV_DPTK_IMP_B1_R2_TAG13,
EM_MOV_RET_SPTK_B1_R2_TAG13,
EM_MOV_RET_SPTK_IMP_B1_R2_TAG13,
EM_MOV_RET_B1_R2_TAG13,
EM_MOV_RET_IMP_B1_R2_TAG13,
EM_MOV_RET_DPTK_B1_R2_TAG13,
EM_MOV_RET_DPTK_IMP_B1_R2_TAG13,
EM_MOV_R1_B2,
EM_MOV_PR_R2_MASK17,
EM_MOV_PR_ROT_IMM44,
EM_MOV_R1_IP,
EM_MOV_R1_PR,
EM_MOV_I_AR3_R2,
EM_MOV_I_AR3_IMM8,
EM_MOV_I_R1_AR3,
EM_ZXT1_R1_R3,
EM_ZXT2_R1_R3,
EM_ZXT4_R1_R3,
EM_SXT1_R1_R3,
EM_SXT2_R1_R3,
EM_SXT4_R1_R3,
EM_CZX1_L_R1_R3,
EM_CZX2_L_R1_R3,
EM_CZX1_R_R1_R3,
EM_CZX2_R_R1_R3,
EM_LD1_R1_R3,
EM_LD1_NT1_R1_R3,
EM_LD1_NTA_R1_R3,
EM_LD2_R1_R3,
EM_LD2_NT1_R1_R3,
EM_LD2_NTA_R1_R3,
EM_LD4_R1_R3,
EM_LD4_NT1_R1_R3,
EM_LD4_NTA_R1_R3,
EM_LD8_R1_R3,
EM_LD8_NT1_R1_R3,
EM_LD8_NTA_R1_R3,
EM_LD1_S_R1_R3,
EM_LD1_S_NT1_R1_R3,
EM_LD1_S_NTA_R1_R3,
EM_LD2_S_R1_R3,
EM_LD2_S_NT1_R1_R3,
EM_LD2_S_NTA_R1_R3,
EM_LD4_S_R1_R3,
EM_LD4_S_NT1_R1_R3,
EM_LD4_S_NTA_R1_R3,
EM_LD8_S_R1_R3,
EM_LD8_S_NT1_R1_R3,
EM_LD8_S_NTA_R1_R3,
EM_LD1_A_R1_R3,
EM_LD1_A_NT1_R1_R3,
EM_LD1_A_NTA_R1_R3,
EM_LD2_A_R1_R3,
EM_LD2_A_NT1_R1_R3,
EM_LD2_A_NTA_R1_R3,
EM_LD4_A_R1_R3,
EM_LD4_A_NT1_R1_R3,
EM_LD4_A_NTA_R1_R3,
EM_LD8_A_R1_R3,
EM_LD8_A_NT1_R1_R3,
EM_LD8_A_NTA_R1_R3,
EM_LD1_SA_R1_R3,
EM_LD1_SA_NT1_R1_R3,
EM_LD1_SA_NTA_R1_R3,
EM_LD2_SA_R1_R3,
EM_LD2_SA_NT1_R1_R3,
EM_LD2_SA_NTA_R1_R3,
EM_LD4_SA_R1_R3,
EM_LD4_SA_NT1_R1_R3,
EM_LD4_SA_NTA_R1_R3,
EM_LD8_SA_R1_R3,
EM_LD8_SA_NT1_R1_R3,
EM_LD8_SA_NTA_R1_R3,
EM_LD1_BIAS_R1_R3,
EM_LD1_BIAS_NT1_R1_R3,
EM_LD1_BIAS_NTA_R1_R3,
EM_LD2_BIAS_R1_R3,
EM_LD2_BIAS_NT1_R1_R3,
EM_LD2_BIAS_NTA_R1_R3,
EM_LD4_BIAS_R1_R3,
EM_LD4_BIAS_NT1_R1_R3,
EM_LD4_BIAS_NTA_R1_R3,
EM_LD8_BIAS_R1_R3,
EM_LD8_BIAS_NT1_R1_R3,
EM_LD8_BIAS_NTA_R1_R3,
EM_LD1_ACQ_R1_R3,
EM_LD1_ACQ_NT1_R1_R3,
EM_LD1_ACQ_NTA_R1_R3,
EM_LD2_ACQ_R1_R3,
EM_LD2_ACQ_NT1_R1_R3,
EM_LD2_ACQ_NTA_R1_R3,
EM_LD4_ACQ_R1_R3,
EM_LD4_ACQ_NT1_R1_R3,
EM_LD4_ACQ_NTA_R1_R3,
EM_LD8_ACQ_R1_R3,
EM_LD8_ACQ_NT1_R1_R3,
EM_LD8_ACQ_NTA_R1_R3,
EM_LD8_FILL_R1_R3,
EM_LD8_FILL_NT1_R1_R3,
EM_LD8_FILL_NTA_R1_R3,
EM_LD1_C_CLR_R1_R3,
EM_LD1_C_CLR_NT1_R1_R3,
EM_LD1_C_CLR_NTA_R1_R3,
EM_LD2_C_CLR_R1_R3,
EM_LD2_C_CLR_NT1_R1_R3,
EM_LD2_C_CLR_NTA_R1_R3,
EM_LD4_C_CLR_R1_R3,
EM_LD4_C_CLR_NT1_R1_R3,
EM_LD4_C_CLR_NTA_R1_R3,
EM_LD8_C_CLR_R1_R3,
EM_LD8_C_CLR_NT1_R1_R3,
EM_LD8_C_CLR_NTA_R1_R3,
EM_LD1_C_NC_R1_R3,
EM_LD1_C_NC_NT1_R1_R3,
EM_LD1_C_NC_NTA_R1_R3,
EM_LD2_C_NC_R1_R3,
EM_LD2_C_NC_NT1_R1_R3,
EM_LD2_C_NC_NTA_R1_R3,
EM_LD4_C_NC_R1_R3,
EM_LD4_C_NC_NT1_R1_R3,
EM_LD4_C_NC_NTA_R1_R3,
EM_LD8_C_NC_R1_R3,
EM_LD8_C_NC_NT1_R1_R3,
EM_LD8_C_NC_NTA_R1_R3,
EM_LD1_C_CLR_ACQ_R1_R3,
EM_LD1_C_CLR_ACQ_NT1_R1_R3,
EM_LD1_C_CLR_ACQ_NTA_R1_R3,
EM_LD2_C_CLR_ACQ_R1_R3,
EM_LD2_C_CLR_ACQ_NT1_R1_R3,
EM_LD2_C_CLR_ACQ_NTA_R1_R3,
EM_LD4_C_CLR_ACQ_R1_R3,
EM_LD4_C_CLR_ACQ_NT1_R1_R3,
EM_LD4_C_CLR_ACQ_NTA_R1_R3,
EM_LD8_C_CLR_ACQ_R1_R3,
EM_LD8_C_CLR_ACQ_NT1_R1_R3,
EM_LD8_C_CLR_ACQ_NTA_R1_R3,
EM_LD1_R1_R3_R2,
EM_LD1_NT1_R1_R3_R2,
EM_LD1_NTA_R1_R3_R2,
EM_LD2_R1_R3_R2,
EM_LD2_NT1_R1_R3_R2,
EM_LD2_NTA_R1_R3_R2,
EM_LD4_R1_R3_R2,
EM_LD4_NT1_R1_R3_R2,
EM_LD4_NTA_R1_R3_R2,
EM_LD8_R1_R3_R2,
EM_LD8_NT1_R1_R3_R2,
EM_LD8_NTA_R1_R3_R2,
EM_LD1_S_R1_R3_R2,
EM_LD1_S_NT1_R1_R3_R2,
EM_LD1_S_NTA_R1_R3_R2,
EM_LD2_S_R1_R3_R2,
EM_LD2_S_NT1_R1_R3_R2,
EM_LD2_S_NTA_R1_R3_R2,
EM_LD4_S_R1_R3_R2,
EM_LD4_S_NT1_R1_R3_R2,
EM_LD4_S_NTA_R1_R3_R2,
EM_LD8_S_R1_R3_R2,
EM_LD8_S_NT1_R1_R3_R2,
EM_LD8_S_NTA_R1_R3_R2,
EM_LD1_A_R1_R3_R2,
EM_LD1_A_NT1_R1_R3_R2,
EM_LD1_A_NTA_R1_R3_R2,
EM_LD2_A_R1_R3_R2,
EM_LD2_A_NT1_R1_R3_R2,
EM_LD2_A_NTA_R1_R3_R2,
EM_LD4_A_R1_R3_R2,
EM_LD4_A_NT1_R1_R3_R2,
EM_LD4_A_NTA_R1_R3_R2,
EM_LD8_A_R1_R3_R2,
EM_LD8_A_NT1_R1_R3_R2,
EM_LD8_A_NTA_R1_R3_R2,
EM_LD1_SA_R1_R3_R2,
EM_LD1_SA_NT1_R1_R3_R2,
EM_LD1_SA_NTA_R1_R3_R2,
EM_LD2_SA_R1_R3_R2,
EM_LD2_SA_NT1_R1_R3_R2,
EM_LD2_SA_NTA_R1_R3_R2,
EM_LD4_SA_R1_R3_R2,
EM_LD4_SA_NT1_R1_R3_R2,
EM_LD4_SA_NTA_R1_R3_R2,
EM_LD8_SA_R1_R3_R2,
EM_LD8_SA_NT1_R1_R3_R2,
EM_LD8_SA_NTA_R1_R3_R2,
EM_LD1_BIAS_R1_R3_R2,
EM_LD1_BIAS_NT1_R1_R3_R2,
EM_LD1_BIAS_NTA_R1_R3_R2,
EM_LD2_BIAS_R1_R3_R2,
EM_LD2_BIAS_NT1_R1_R3_R2,
EM_LD2_BIAS_NTA_R1_R3_R2,
EM_LD4_BIAS_R1_R3_R2,
EM_LD4_BIAS_NT1_R1_R3_R2,
EM_LD4_BIAS_NTA_R1_R3_R2,
EM_LD8_BIAS_R1_R3_R2,
EM_LD8_BIAS_NT1_R1_R3_R2,
EM_LD8_BIAS_NTA_R1_R3_R2,
EM_LD1_ACQ_R1_R3_R2,
EM_LD1_ACQ_NT1_R1_R3_R2,
EM_LD1_ACQ_NTA_R1_R3_R2,
EM_LD2_ACQ_R1_R3_R2,
EM_LD2_ACQ_NT1_R1_R3_R2,
EM_LD2_ACQ_NTA_R1_R3_R2,
EM_LD4_ACQ_R1_R3_R2,
EM_LD4_ACQ_NT1_R1_R3_R2,
EM_LD4_ACQ_NTA_R1_R3_R2,
EM_LD8_ACQ_R1_R3_R2,
EM_LD8_ACQ_NT1_R1_R3_R2,
EM_LD8_ACQ_NTA_R1_R3_R2,
EM_LD8_FILL_R1_R3_R2,
EM_LD8_FILL_NT1_R1_R3_R2,
EM_LD8_FILL_NTA_R1_R3_R2,
EM_LD1_C_CLR_R1_R3_R2,
EM_LD1_C_CLR_NT1_R1_R3_R2,
EM_LD1_C_CLR_NTA_R1_R3_R2,
EM_LD2_C_CLR_R1_R3_R2,
EM_LD2_C_CLR_NT1_R1_R3_R2,
EM_LD2_C_CLR_NTA_R1_R3_R2,
EM_LD4_C_CLR_R1_R3_R2,
EM_LD4_C_CLR_NT1_R1_R3_R2,
EM_LD4_C_CLR_NTA_R1_R3_R2,
EM_LD8_C_CLR_R1_R3_R2,
EM_LD8_C_CLR_NT1_R1_R3_R2,
EM_LD8_C_CLR_NTA_R1_R3_R2,
EM_LD1_C_NC_R1_R3_R2,
EM_LD1_C_NC_NT1_R1_R3_R2,
EM_LD1_C_NC_NTA_R1_R3_R2,
EM_LD2_C_NC_R1_R3_R2,
EM_LD2_C_NC_NT1_R1_R3_R2,
EM_LD2_C_NC_NTA_R1_R3_R2,
EM_LD4_C_NC_R1_R3_R2,
EM_LD4_C_NC_NT1_R1_R3_R2,
EM_LD4_C_NC_NTA_R1_R3_R2,
EM_LD8_C_NC_R1_R3_R2,
EM_LD8_C_NC_NT1_R1_R3_R2,
EM_LD8_C_NC_NTA_R1_R3_R2,
EM_LD1_C_CLR_ACQ_R1_R3_R2,
EM_LD1_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD1_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD2_C_CLR_ACQ_R1_R3_R2,
EM_LD2_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD2_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD4_C_CLR_ACQ_R1_R3_R2,
EM_LD4_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD4_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD8_C_CLR_ACQ_R1_R3_R2,
EM_LD8_C_CLR_ACQ_NT1_R1_R3_R2,
EM_LD8_C_CLR_ACQ_NTA_R1_R3_R2,
EM_LD1_R1_R3_IMM9,
EM_LD1_NT1_R1_R3_IMM9,
EM_LD1_NTA_R1_R3_IMM9,
EM_LD2_R1_R3_IMM9,
EM_LD2_NT1_R1_R3_IMM9,
EM_LD2_NTA_R1_R3_IMM9,
EM_LD4_R1_R3_IMM9,
EM_LD4_NT1_R1_R3_IMM9,
EM_LD4_NTA_R1_R3_IMM9,
EM_LD8_R1_R3_IMM9,
EM_LD8_NT1_R1_R3_IMM9,
EM_LD8_NTA_R1_R3_IMM9,
EM_LD1_S_R1_R3_IMM9,
EM_LD1_S_NT1_R1_R3_IMM9,
EM_LD1_S_NTA_R1_R3_IMM9,
EM_LD2_S_R1_R3_IMM9,
EM_LD2_S_NT1_R1_R3_IMM9,
EM_LD2_S_NTA_R1_R3_IMM9,
EM_LD4_S_R1_R3_IMM9,
EM_LD4_S_NT1_R1_R3_IMM9,
EM_LD4_S_NTA_R1_R3_IMM9,
EM_LD8_S_R1_R3_IMM9,
EM_LD8_S_NT1_R1_R3_IMM9,
EM_LD8_S_NTA_R1_R3_IMM9,
EM_LD1_A_R1_R3_IMM9,
EM_LD1_A_NT1_R1_R3_IMM9,
EM_LD1_A_NTA_R1_R3_IMM9,
EM_LD2_A_R1_R3_IMM9,
EM_LD2_A_NT1_R1_R3_IMM9,
EM_LD2_A_NTA_R1_R3_IMM9,
EM_LD4_A_R1_R3_IMM9,
EM_LD4_A_NT1_R1_R3_IMM9,
EM_LD4_A_NTA_R1_R3_IMM9,
EM_LD8_A_R1_R3_IMM9,
EM_LD8_A_NT1_R1_R3_IMM9,
EM_LD8_A_NTA_R1_R3_IMM9,
EM_LD1_SA_R1_R3_IMM9,
EM_LD1_SA_NT1_R1_R3_IMM9,
EM_LD1_SA_NTA_R1_R3_IMM9,
EM_LD2_SA_R1_R3_IMM9,
EM_LD2_SA_NT1_R1_R3_IMM9,
EM_LD2_SA_NTA_R1_R3_IMM9,
EM_LD4_SA_R1_R3_IMM9,
EM_LD4_SA_NT1_R1_R3_IMM9,
EM_LD4_SA_NTA_R1_R3_IMM9,
EM_LD8_SA_R1_R3_IMM9,
EM_LD8_SA_NT1_R1_R3_IMM9,
EM_LD8_SA_NTA_R1_R3_IMM9,
EM_LD1_BIAS_R1_R3_IMM9,
EM_LD1_BIAS_NT1_R1_R3_IMM9,
EM_LD1_BIAS_NTA_R1_R3_IMM9,
EM_LD2_BIAS_R1_R3_IMM9,
EM_LD2_BIAS_NT1_R1_R3_IMM9,
EM_LD2_BIAS_NTA_R1_R3_IMM9,
EM_LD4_BIAS_R1_R3_IMM9,
EM_LD4_BIAS_NT1_R1_R3_IMM9,
EM_LD4_BIAS_NTA_R1_R3_IMM9,
EM_LD8_BIAS_R1_R3_IMM9,
EM_LD8_BIAS_NT1_R1_R3_IMM9,
EM_LD8_BIAS_NTA_R1_R3_IMM9,
EM_LD1_ACQ_R1_R3_IMM9,
EM_LD1_ACQ_NT1_R1_R3_IMM9,
EM_LD1_ACQ_NTA_R1_R3_IMM9,
EM_LD2_ACQ_R1_R3_IMM9,
EM_LD2_ACQ_NT1_R1_R3_IMM9,
EM_LD2_ACQ_NTA_R1_R3_IMM9,
EM_LD4_ACQ_R1_R3_IMM9,
EM_LD4_ACQ_NT1_R1_R3_IMM9,
EM_LD4_ACQ_NTA_R1_R3_IMM9,
EM_LD8_ACQ_R1_R3_IMM9,
EM_LD8_ACQ_NT1_R1_R3_IMM9,
EM_LD8_ACQ_NTA_R1_R3_IMM9,
EM_LD8_FILL_R1_R3_IMM9,
EM_LD8_FILL_NT1_R1_R3_IMM9,
EM_LD8_FILL_NTA_R1_R3_IMM9,
EM_LD1_C_CLR_R1_R3_IMM9,
EM_LD1_C_CLR_NT1_R1_R3_IMM9,
EM_LD1_C_CLR_NTA_R1_R3_IMM9,
EM_LD2_C_CLR_R1_R3_IMM9,
EM_LD2_C_CLR_NT1_R1_R3_IMM9,
EM_LD2_C_CLR_NTA_R1_R3_IMM9,
EM_LD4_C_CLR_R1_R3_IMM9,
EM_LD4_C_CLR_NT1_R1_R3_IMM9,
EM_LD4_C_CLR_NTA_R1_R3_IMM9,
EM_LD8_C_CLR_R1_R3_IMM9,
EM_LD8_C_CLR_NT1_R1_R3_IMM9,
EM_LD8_C_CLR_NTA_R1_R3_IMM9,
EM_LD1_C_NC_R1_R3_IMM9,
EM_LD1_C_NC_NT1_R1_R3_IMM9,
EM_LD1_C_NC_NTA_R1_R3_IMM9,
EM_LD2_C_NC_R1_R3_IMM9,
EM_LD2_C_NC_NT1_R1_R3_IMM9,
EM_LD2_C_NC_NTA_R1_R3_IMM9,
EM_LD4_C_NC_R1_R3_IMM9,
EM_LD4_C_NC_NT1_R1_R3_IMM9,
EM_LD4_C_NC_NTA_R1_R3_IMM9,
EM_LD8_C_NC_R1_R3_IMM9,
EM_LD8_C_NC_NT1_R1_R3_IMM9,
EM_LD8_C_NC_NTA_R1_R3_IMM9,
EM_LD1_C_CLR_ACQ_R1_R3_IMM9,
EM_LD1_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD1_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_LD2_C_CLR_ACQ_R1_R3_IMM9,
EM_LD2_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD2_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_LD4_C_CLR_ACQ_R1_R3_IMM9,
EM_LD4_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD4_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_LD8_C_CLR_ACQ_R1_R3_IMM9,
EM_LD8_C_CLR_ACQ_NT1_R1_R3_IMM9,
EM_LD8_C_CLR_ACQ_NTA_R1_R3_IMM9,
EM_ST1_R3_R2,
EM_ST1_NTA_R3_R2,
EM_ST2_R3_R2,
EM_ST2_NTA_R3_R2,
EM_ST4_R3_R2,
EM_ST4_NTA_R3_R2,
EM_ST8_R3_R2,
EM_ST8_NTA_R3_R2,
EM_ST1_REL_R3_R2,
EM_ST1_REL_NTA_R3_R2,
EM_ST2_REL_R3_R2,
EM_ST2_REL_NTA_R3_R2,
EM_ST4_REL_R3_R2,
EM_ST4_REL_NTA_R3_R2,
EM_ST8_REL_R3_R2,
EM_ST8_REL_NTA_R3_R2,
EM_ST8_SPILL_R3_R2,
EM_ST8_SPILL_NTA_R3_R2,
EM_ST1_R3_R2_IMM9,
EM_ST1_NTA_R3_R2_IMM9,
EM_ST2_R3_R2_IMM9,
EM_ST2_NTA_R3_R2_IMM9,
EM_ST4_R3_R2_IMM9,
EM_ST4_NTA_R3_R2_IMM9,
EM_ST8_R3_R2_IMM9,
EM_ST8_NTA_R3_R2_IMM9,
EM_ST1_REL_R3_R2_IMM9,
EM_ST1_REL_NTA_R3_R2_IMM9,
EM_ST2_REL_R3_R2_IMM9,
EM_ST2_REL_NTA_R3_R2_IMM9,
EM_ST4_REL_R3_R2_IMM9,
EM_ST4_REL_NTA_R3_R2_IMM9,
EM_ST8_REL_R3_R2_IMM9,
EM_ST8_REL_NTA_R3_R2_IMM9,
EM_ST8_SPILL_R3_R2_IMM9,
EM_ST8_SPILL_NTA_R3_R2_IMM9,
EM_LDFS_F1_R3,
EM_LDFS_NT1_F1_R3,
EM_LDFS_NTA_F1_R3,
EM_LDFD_F1_R3,
EM_LDFD_NT1_F1_R3,
EM_LDFD_NTA_F1_R3,
EM_LDF8_F1_R3,
EM_LDF8_NT1_F1_R3,
EM_LDF8_NTA_F1_R3,
EM_LDFE_F1_R3,
EM_LDFE_NT1_F1_R3,
EM_LDFE_NTA_F1_R3,
EM_LDFS_S_F1_R3,
EM_LDFS_S_NT1_F1_R3,
EM_LDFS_S_NTA_F1_R3,
EM_LDFD_S_F1_R3,
EM_LDFD_S_NT1_F1_R3,
EM_LDFD_S_NTA_F1_R3,
EM_LDF8_S_F1_R3,
EM_LDF8_S_NT1_F1_R3,
EM_LDF8_S_NTA_F1_R3,
EM_LDFE_S_F1_R3,
EM_LDFE_S_NT1_F1_R3,
EM_LDFE_S_NTA_F1_R3,
EM_LDFS_A_F1_R3,
EM_LDFS_A_NT1_F1_R3,
EM_LDFS_A_NTA_F1_R3,
EM_LDFD_A_F1_R3,
EM_LDFD_A_NT1_F1_R3,
EM_LDFD_A_NTA_F1_R3,
EM_LDF8_A_F1_R3,
EM_LDF8_A_NT1_F1_R3,
EM_LDF8_A_NTA_F1_R3,
EM_LDFE_A_F1_R3,
EM_LDFE_A_NT1_F1_R3,
EM_LDFE_A_NTA_F1_R3,
EM_LDFS_SA_F1_R3,
EM_LDFS_SA_NT1_F1_R3,
EM_LDFS_SA_NTA_F1_R3,
EM_LDFD_SA_F1_R3,
EM_LDFD_SA_NT1_F1_R3,
EM_LDFD_SA_NTA_F1_R3,
EM_LDF8_SA_F1_R3,
EM_LDF8_SA_NT1_F1_R3,
EM_LDF8_SA_NTA_F1_R3,
EM_LDFE_SA_F1_R3,
EM_LDFE_SA_NT1_F1_R3,
EM_LDFE_SA_NTA_F1_R3,
EM_LDF_FILL_F1_R3,
EM_LDF_FILL_NT1_F1_R3,
EM_LDF_FILL_NTA_F1_R3,
EM_LDFS_C_CLR_F1_R3,
EM_LDFS_C_CLR_NT1_F1_R3,
EM_LDFS_C_CLR_NTA_F1_R3,
EM_LDFD_C_CLR_F1_R3,
EM_LDFD_C_CLR_NT1_F1_R3,
EM_LDFD_C_CLR_NTA_F1_R3,
EM_LDF8_C_CLR_F1_R3,
EM_LDF8_C_CLR_NT1_F1_R3,
EM_LDF8_C_CLR_NTA_F1_R3,
EM_LDFE_C_CLR_F1_R3,
EM_LDFE_C_CLR_NT1_F1_R3,
EM_LDFE_C_CLR_NTA_F1_R3,
EM_LDFS_C_NC_F1_R3,
EM_LDFS_C_NC_NT1_F1_R3,
EM_LDFS_C_NC_NTA_F1_R3,
EM_LDFD_C_NC_F1_R3,
EM_LDFD_C_NC_NT1_F1_R3,
EM_LDFD_C_NC_NTA_F1_R3,
EM_LDF8_C_NC_F1_R3,
EM_LDF8_C_NC_NT1_F1_R3,
EM_LDF8_C_NC_NTA_F1_R3,
EM_LDFE_C_NC_F1_R3,
EM_LDFE_C_NC_NT1_F1_R3,
EM_LDFE_C_NC_NTA_F1_R3,
EM_LDFS_F1_R3_R2,
EM_LDFS_NT1_F1_R3_R2,
EM_LDFS_NTA_F1_R3_R2,
EM_LDFD_F1_R3_R2,
EM_LDFD_NT1_F1_R3_R2,
EM_LDFD_NTA_F1_R3_R2,
EM_LDF8_F1_R3_R2,
EM_LDF8_NT1_F1_R3_R2,
EM_LDF8_NTA_F1_R3_R2,
EM_LDFE_F1_R3_R2,
EM_LDFE_NT1_F1_R3_R2,
EM_LDFE_NTA_F1_R3_R2,
EM_LDFS_S_F1_R3_R2,
EM_LDFS_S_NT1_F1_R3_R2,
EM_LDFS_S_NTA_F1_R3_R2,
EM_LDFD_S_F1_R3_R2,
EM_LDFD_S_NT1_F1_R3_R2,
EM_LDFD_S_NTA_F1_R3_R2,
EM_LDF8_S_F1_R3_R2,
EM_LDF8_S_NT1_F1_R3_R2,
EM_LDF8_S_NTA_F1_R3_R2,
EM_LDFE_S_F1_R3_R2,
EM_LDFE_S_NT1_F1_R3_R2,
EM_LDFE_S_NTA_F1_R3_R2,
EM_LDFS_A_F1_R3_R2,
EM_LDFS_A_NT1_F1_R3_R2,
EM_LDFS_A_NTA_F1_R3_R2,
EM_LDFD_A_F1_R3_R2,
EM_LDFD_A_NT1_F1_R3_R2,
EM_LDFD_A_NTA_F1_R3_R2,
EM_LDF8_A_F1_R3_R2,
EM_LDF8_A_NT1_F1_R3_R2,
EM_LDF8_A_NTA_F1_R3_R2,
EM_LDFE_A_F1_R3_R2,
EM_LDFE_A_NT1_F1_R3_R2,
EM_LDFE_A_NTA_F1_R3_R2,
EM_LDFS_SA_F1_R3_R2,
EM_LDFS_SA_NT1_F1_R3_R2,
EM_LDFS_SA_NTA_F1_R3_R2,
EM_LDFD_SA_F1_R3_R2,
EM_LDFD_SA_NT1_F1_R3_R2,
EM_LDFD_SA_NTA_F1_R3_R2,
EM_LDF8_SA_F1_R3_R2,
EM_LDF8_SA_NT1_F1_R3_R2,
EM_LDF8_SA_NTA_F1_R3_R2,
EM_LDFE_SA_F1_R3_R2,
EM_LDFE_SA_NT1_F1_R3_R2,
EM_LDFE_SA_NTA_F1_R3_R2,
EM_LDF_FILL_F1_R3_R2,
EM_LDF_FILL_NT1_F1_R3_R2,
EM_LDF_FILL_NTA_F1_R3_R2,
EM_LDFS_C_CLR_F1_R3_R2,
EM_LDFS_C_CLR_NT1_F1_R3_R2,
EM_LDFS_C_CLR_NTA_F1_R3_R2,
EM_LDFD_C_CLR_F1_R3_R2,
EM_LDFD_C_CLR_NT1_F1_R3_R2,
EM_LDFD_C_CLR_NTA_F1_R3_R2,
EM_LDF8_C_CLR_F1_R3_R2,
EM_LDF8_C_CLR_NT1_F1_R3_R2,
EM_LDF8_C_CLR_NTA_F1_R3_R2,
EM_LDFE_C_CLR_F1_R3_R2,
EM_LDFE_C_CLR_NT1_F1_R3_R2,
EM_LDFE_C_CLR_NTA_F1_R3_R2,
EM_LDFS_C_NC_F1_R3_R2,
EM_LDFS_C_NC_NT1_F1_R3_R2,
EM_LDFS_C_NC_NTA_F1_R3_R2,
EM_LDFD_C_NC_F1_R3_R2,
EM_LDFD_C_NC_NT1_F1_R3_R2,
EM_LDFD_C_NC_NTA_F1_R3_R2,
EM_LDF8_C_NC_F1_R3_R2,
EM_LDF8_C_NC_NT1_F1_R3_R2,
EM_LDF8_C_NC_NTA_F1_R3_R2,
EM_LDFE_C_NC_F1_R3_R2,
EM_LDFE_C_NC_NT1_F1_R3_R2,
EM_LDFE_C_NC_NTA_F1_R3_R2,
EM_LDFS_F1_R3_IMM9,
EM_LDFS_NT1_F1_R3_IMM9,
EM_LDFS_NTA_F1_R3_IMM9,
EM_LDFD_F1_R3_IMM9,
EM_LDFD_NT1_F1_R3_IMM9,
EM_LDFD_NTA_F1_R3_IMM9,
EM_LDF8_F1_R3_IMM9,
EM_LDF8_NT1_F1_R3_IMM9,
EM_LDF8_NTA_F1_R3_IMM9,
EM_LDFE_F1_R3_IMM9,
EM_LDFE_NT1_F1_R3_IMM9,
EM_LDFE_NTA_F1_R3_IMM9,
EM_LDFS_S_F1_R3_IMM9,
EM_LDFS_S_NT1_F1_R3_IMM9,
EM_LDFS_S_NTA_F1_R3_IMM9,
EM_LDFD_S_F1_R3_IMM9,
EM_LDFD_S_NT1_F1_R3_IMM9,
EM_LDFD_S_NTA_F1_R3_IMM9,
EM_LDF8_S_F1_R3_IMM9,
EM_LDF8_S_NT1_F1_R3_IMM9,
EM_LDF8_S_NTA_F1_R3_IMM9,
EM_LDFE_S_F1_R3_IMM9,
EM_LDFE_S_NT1_F1_R3_IMM9,
EM_LDFE_S_NTA_F1_R3_IMM9,
EM_LDFS_A_F1_R3_IMM9,
EM_LDFS_A_NT1_F1_R3_IMM9,
EM_LDFS_A_NTA_F1_R3_IMM9,
EM_LDFD_A_F1_R3_IMM9,
EM_LDFD_A_NT1_F1_R3_IMM9,
EM_LDFD_A_NTA_F1_R3_IMM9,
EM_LDF8_A_F1_R3_IMM9,
EM_LDF8_A_NT1_F1_R3_IMM9,
EM_LDF8_A_NTA_F1_R3_IMM9,
EM_LDFE_A_F1_R3_IMM9,
EM_LDFE_A_NT1_F1_R3_IMM9,
EM_LDFE_A_NTA_F1_R3_IMM9,
EM_LDFS_SA_F1_R3_IMM9,
EM_LDFS_SA_NT1_F1_R3_IMM9,
EM_LDFS_SA_NTA_F1_R3_IMM9,
EM_LDFD_SA_F1_R3_IMM9,
EM_LDFD_SA_NT1_F1_R3_IMM9,
EM_LDFD_SA_NTA_F1_R3_IMM9,
EM_LDF8_SA_F1_R3_IMM9,
EM_LDF8_SA_NT1_F1_R3_IMM9,
EM_LDF8_SA_NTA_F1_R3_IMM9,
EM_LDFE_SA_F1_R3_IMM9,
EM_LDFE_SA_NT1_F1_R3_IMM9,
EM_LDFE_SA_NTA_F1_R3_IMM9,
EM_LDF_FILL_F1_R3_IMM9,
EM_LDF_FILL_NT1_F1_R3_IMM9,
EM_LDF_FILL_NTA_F1_R3_IMM9,
EM_LDFS_C_CLR_F1_R3_IMM9,
EM_INST1_LAST
} Inst_id_t1;

typedef enum Inst_id_e2
{
EM_LDFS_C_CLR_NT1_F1_R3_IMM9 = EM_INST1_LAST,
EM_LDFS_C_CLR_NTA_F1_R3_IMM9,
EM_LDFD_C_CLR_F1_R3_IMM9,
EM_LDFD_C_CLR_NT1_F1_R3_IMM9,
EM_LDFD_C_CLR_NTA_F1_R3_IMM9,
EM_LDF8_C_CLR_F1_R3_IMM9,
EM_LDF8_C_CLR_NT1_F1_R3_IMM9,
EM_LDF8_C_CLR_NTA_F1_R3_IMM9,
EM_LDFE_C_CLR_F1_R3_IMM9,
EM_LDFE_C_CLR_NT1_F1_R3_IMM9,
EM_LDFE_C_CLR_NTA_F1_R3_IMM9,
EM_LDFS_C_NC_F1_R3_IMM9,
EM_LDFS_C_NC_NT1_F1_R3_IMM9,
EM_LDFS_C_NC_NTA_F1_R3_IMM9,
EM_LDFD_C_NC_F1_R3_IMM9,
EM_LDFD_C_NC_NT1_F1_R3_IMM9,
EM_LDFD_C_NC_NTA_F1_R3_IMM9,
EM_LDF8_C_NC_F1_R3_IMM9,
EM_LDF8_C_NC_NT1_F1_R3_IMM9,
EM_LDF8_C_NC_NTA_F1_R3_IMM9,
EM_LDFE_C_NC_F1_R3_IMM9,
EM_LDFE_C_NC_NT1_F1_R3_IMM9,
EM_LDFE_C_NC_NTA_F1_R3_IMM9,
EM_STFS_R3_F2,
EM_STFS_NTA_R3_F2,
EM_STFD_R3_F2,
EM_STFD_NTA_R3_F2,
EM_STF8_R3_F2,
EM_STF8_NTA_R3_F2,
EM_STFE_R3_F2,
EM_STFE_NTA_R3_F2,
EM_STF_SPILL_R3_F2,
EM_STF_SPILL_NTA_R3_F2,
EM_STFS_R3_F2_IMM9,
EM_STFS_NTA_R3_F2_IMM9,
EM_STFD_R3_F2_IMM9,
EM_STFD_NTA_R3_F2_IMM9,
EM_STF8_R3_F2_IMM9,
EM_STF8_NTA_R3_F2_IMM9,
EM_STFE_R3_F2_IMM9,
EM_STFE_NTA_R3_F2_IMM9,
EM_STF_SPILL_R3_F2_IMM9,
EM_STF_SPILL_NTA_R3_F2_IMM9,
EM_LDFPS_F1_F2_R3,
EM_LDFPS_NT1_F1_F2_R3,
EM_LDFPS_NTA_F1_F2_R3,
EM_LDFPD_F1_F2_R3,
EM_LDFPD_NT1_F1_F2_R3,
EM_LDFPD_NTA_F1_F2_R3,
EM_LDFP8_F1_F2_R3,
EM_LDFP8_NT1_F1_F2_R3,
EM_LDFP8_NTA_F1_F2_R3,
EM_LDFPS_S_F1_F2_R3,
EM_LDFPS_S_NT1_F1_F2_R3,
EM_LDFPS_S_NTA_F1_F2_R3,
EM_LDFPD_S_F1_F2_R3,
EM_LDFPD_S_NT1_F1_F2_R3,
EM_LDFPD_S_NTA_F1_F2_R3,
EM_LDFP8_S_F1_F2_R3,
EM_LDFP8_S_NT1_F1_F2_R3,
EM_LDFP8_S_NTA_F1_F2_R3,
EM_LDFPS_A_F1_F2_R3,
EM_LDFPS_A_NT1_F1_F2_R3,
EM_LDFPS_A_NTA_F1_F2_R3,
EM_LDFPD_A_F1_F2_R3,
EM_LDFPD_A_NT1_F1_F2_R3,
EM_LDFPD_A_NTA_F1_F2_R3,
EM_LDFP8_A_F1_F2_R3,
EM_LDFP8_A_NT1_F1_F2_R3,
EM_LDFP8_A_NTA_F1_F2_R3,
EM_LDFPS_SA_F1_F2_R3,
EM_LDFPS_SA_NT1_F1_F2_R3,
EM_LDFPS_SA_NTA_F1_F2_R3,
EM_LDFPD_SA_F1_F2_R3,
EM_LDFPD_SA_NT1_F1_F2_R3,
EM_LDFPD_SA_NTA_F1_F2_R3,
EM_LDFP8_SA_F1_F2_R3,
EM_LDFP8_SA_NT1_F1_F2_R3,
EM_LDFP8_SA_NTA_F1_F2_R3,
EM_LDFPS_C_CLR_F1_F2_R3,
EM_LDFPS_C_CLR_NT1_F1_F2_R3,
EM_LDFPS_C_CLR_NTA_F1_F2_R3,
EM_LDFPD_C_CLR_F1_F2_R3,
EM_LDFPD_C_CLR_NT1_F1_F2_R3,
EM_LDFPD_C_CLR_NTA_F1_F2_R3,
EM_LDFP8_C_CLR_F1_F2_R3,
EM_LDFP8_C_CLR_NT1_F1_F2_R3,
EM_LDFP8_C_CLR_NTA_F1_F2_R3,
EM_LDFPS_C_NC_F1_F2_R3,
EM_LDFPS_C_NC_NT1_F1_F2_R3,
EM_LDFPS_C_NC_NTA_F1_F2_R3,
EM_LDFPD_C_NC_F1_F2_R3,
EM_LDFPD_C_NC_NT1_F1_F2_R3,
EM_LDFPD_C_NC_NTA_F1_F2_R3,
EM_LDFP8_C_NC_F1_F2_R3,
EM_LDFP8_C_NC_NT1_F1_F2_R3,
EM_LDFP8_C_NC_NTA_F1_F2_R3,
EM_LDFPS_F1_F2_R3_8,
EM_LDFPS_NT1_F1_F2_R3_8,
EM_LDFPS_NTA_F1_F2_R3_8,
EM_LDFPD_F1_F2_R3_16,
EM_LDFPD_NT1_F1_F2_R3_16,
EM_LDFPD_NTA_F1_F2_R3_16,
EM_LDFP8_F1_F2_R3_16,
EM_LDFP8_NT1_F1_F2_R3_16,
EM_LDFP8_NTA_F1_F2_R3_16,
EM_LDFPS_S_F1_F2_R3_8,
EM_LDFPS_S_NT1_F1_F2_R3_8,
EM_LDFPS_S_NTA_F1_F2_R3_8,
EM_LDFPD_S_F1_F2_R3_16,
EM_LDFPD_S_NT1_F1_F2_R3_16,
EM_LDFPD_S_NTA_F1_F2_R3_16,
EM_LDFP8_S_F1_F2_R3_16,
EM_LDFP8_S_NT1_F1_F2_R3_16,
EM_LDFP8_S_NTA_F1_F2_R3_16,
EM_LDFPS_A_F1_F2_R3_8,
EM_LDFPS_A_NT1_F1_F2_R3_8,
EM_LDFPS_A_NTA_F1_F2_R3_8,
EM_LDFPD_A_F1_F2_R3_16,
EM_LDFPD_A_NT1_F1_F2_R3_16,
EM_LDFPD_A_NTA_F1_F2_R3_16,
EM_LDFP8_A_F1_F2_R3_16,
EM_LDFP8_A_NT1_F1_F2_R3_16,
EM_LDFP8_A_NTA_F1_F2_R3_16,
EM_LDFPS_SA_F1_F2_R3_8,
EM_LDFPS_SA_NT1_F1_F2_R3_8,
EM_LDFPS_SA_NTA_F1_F2_R3_8,
EM_LDFPD_SA_F1_F2_R3_16,
EM_LDFPD_SA_NT1_F1_F2_R3_16,
EM_LDFPD_SA_NTA_F1_F2_R3_16,
EM_LDFP8_SA_F1_F2_R3_16,
EM_LDFP8_SA_NT1_F1_F2_R3_16,
EM_LDFP8_SA_NTA_F1_F2_R3_16,
EM_LDFPS_C_CLR_F1_F2_R3_8,
EM_LDFPS_C_CLR_NT1_F1_F2_R3_8,
EM_LDFPS_C_CLR_NTA_F1_F2_R3_8,
EM_LDFPD_C_CLR_F1_F2_R3_16,
EM_LDFPD_C_CLR_NT1_F1_F2_R3_16,
EM_LDFPD_C_CLR_NTA_F1_F2_R3_16,
EM_LDFP8_C_CLR_F1_F2_R3_16,
EM_LDFP8_C_CLR_NT1_F1_F2_R3_16,
EM_LDFP8_C_CLR_NTA_F1_F2_R3_16,
EM_LDFPS_C_NC_F1_F2_R3_8,
EM_LDFPS_C_NC_NT1_F1_F2_R3_8,
EM_LDFPS_C_NC_NTA_F1_F2_R3_8,
EM_LDFPD_C_NC_F1_F2_R3_16,
EM_LDFPD_C_NC_NT1_F1_F2_R3_16,
EM_LDFPD_C_NC_NTA_F1_F2_R3_16,
EM_LDFP8_C_NC_F1_F2_R3_16,
EM_LDFP8_C_NC_NT1_F1_F2_R3_16,
EM_LDFP8_C_NC_NTA_F1_F2_R3_16,
EM_LFETCH_R3,
EM_LFETCH_NT1_R3,
EM_LFETCH_NT2_R3,
EM_LFETCH_NTA_R3,
EM_LFETCH_EXCL_R3,
EM_LFETCH_EXCL_NT1_R3,
EM_LFETCH_EXCL_NT2_R3,
EM_LFETCH_EXCL_NTA_R3,
EM_LFETCH_FAULT_R3,
EM_LFETCH_FAULT_NT1_R3,
EM_LFETCH_FAULT_NT2_R3,
EM_LFETCH_FAULT_NTA_R3,
EM_LFETCH_FAULT_EXCL_R3,
EM_LFETCH_FAULT_EXCL_NT1_R3,
EM_LFETCH_FAULT_EXCL_NT2_R3,
EM_LFETCH_FAULT_EXCL_NTA_R3,
EM_LFETCH_R3_R2,
EM_LFETCH_NT1_R3_R2,
EM_LFETCH_NT2_R3_R2,
EM_LFETCH_NTA_R3_R2,
EM_LFETCH_EXCL_R3_R2,
EM_LFETCH_EXCL_NT1_R3_R2,
EM_LFETCH_EXCL_NT2_R3_R2,
EM_LFETCH_EXCL_NTA_R3_R2,
EM_LFETCH_FAULT_R3_R2,
EM_LFETCH_FAULT_NT1_R3_R2,
EM_LFETCH_FAULT_NT2_R3_R2,
EM_LFETCH_FAULT_NTA_R3_R2,
EM_LFETCH_FAULT_EXCL_R3_R2,
EM_LFETCH_FAULT_EXCL_NT1_R3_R2,
EM_LFETCH_FAULT_EXCL_NT2_R3_R2,
EM_LFETCH_FAULT_EXCL_NTA_R3_R2,
EM_LFETCH_R3_IMM9,
EM_LFETCH_NT1_R3_IMM9,
EM_LFETCH_NT2_R3_IMM9,
EM_LFETCH_NTA_R3_IMM9,
EM_LFETCH_EXCL_R3_IMM9,
EM_LFETCH_EXCL_NT1_R3_IMM9,
EM_LFETCH_EXCL_NT2_R3_IMM9,
EM_LFETCH_EXCL_NTA_R3_IMM9,
EM_LFETCH_FAULT_R3_IMM9,
EM_LFETCH_FAULT_NT1_R3_IMM9,
EM_LFETCH_FAULT_NT2_R3_IMM9,
EM_LFETCH_FAULT_NTA_R3_IMM9,
EM_LFETCH_FAULT_EXCL_R3_IMM9,
EM_LFETCH_FAULT_EXCL_NT1_R3_IMM9,
EM_LFETCH_FAULT_EXCL_NT2_R3_IMM9,
EM_LFETCH_FAULT_EXCL_NTA_R3_IMM9,
EM_CMPXCHG1_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_ACQ_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_ACQ_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_ACQ_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG1_REL_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG2_REL_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG4_REL_NTA_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_REL_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_REL_NT1_R1_R3_R2_AR_CCV,
EM_CMPXCHG8_REL_NTA_R1_R3_R2_AR_CCV,
EM_XCHG1_R1_R3_R2,
EM_XCHG1_NT1_R1_R3_R2,
EM_XCHG1_NTA_R1_R3_R2,
EM_XCHG2_R1_R3_R2,
EM_XCHG2_NT1_R1_R3_R2,
EM_XCHG2_NTA_R1_R3_R2,
EM_XCHG4_R1_R3_R2,
EM_XCHG4_NT1_R1_R3_R2,
EM_XCHG4_NTA_R1_R3_R2,
EM_XCHG8_R1_R3_R2,
EM_XCHG8_NT1_R1_R3_R2,
EM_XCHG8_NTA_R1_R3_R2,
EM_FETCHADD4_ACQ_R1_R3_INC3,
EM_FETCHADD4_ACQ_NT1_R1_R3_INC3,
EM_FETCHADD4_ACQ_NTA_R1_R3_INC3,
EM_FETCHADD8_ACQ_R1_R3_INC3,
EM_FETCHADD8_ACQ_NT1_R1_R3_INC3,
EM_FETCHADD8_ACQ_NTA_R1_R3_INC3,
EM_FETCHADD4_REL_R1_R3_INC3,
EM_FETCHADD4_REL_NT1_R1_R3_INC3,
EM_FETCHADD4_REL_NTA_R1_R3_INC3,
EM_FETCHADD8_REL_R1_R3_INC3,
EM_FETCHADD8_REL_NT1_R1_R3_INC3,
EM_FETCHADD8_REL_NTA_R1_R3_INC3,
EM_SETF_SIG_F1_R2,
EM_SETF_EXP_F1_R2,
EM_SETF_S_F1_R2,
EM_SETF_D_F1_R2,
EM_GETF_SIG_R1_F2,
EM_GETF_EXP_R1_F2,
EM_GETF_S_R1_F2,
EM_GETF_D_R1_F2,
EM_CHK_S_M_R2_TARGET25,
EM_CHK_S_F2_TARGET25,
EM_CHK_A_NC_R1_TARGET25,
EM_CHK_A_CLR_R1_TARGET25,
EM_CHK_A_NC_F1_TARGET25,
EM_CHK_A_CLR_F1_TARGET25,
EM_INVALA,
EM_FWB,
EM_MF,
EM_MF_A,
EM_SRLZ_D,
EM_SRLZ_I,
EM_SYNC_I,
EM_FLUSHRS,
EM_LOADRS,
EM_INVALA_E_R1,
EM_INVALA_E_F1,
EM_FC_R3,
EM_PTC_E_R3,
EM_MOV_M_AR3_R2,
EM_MOV_M_AR3_IMM8,
EM_MOV_M_R1_AR3,
EM_MOV_CR3_R2,
EM_MOV_R1_CR3,
EM_ALLOC_R1_AR_PFS_I_L_O_R,
EM_MOV_PSR_L_R2,
EM_MOV_PSR_UM_R2,
EM_MOV_R1_PSR,
EM_MOV_R1_PSR_UM,
EM_BREAK_M_IMM21,
EM_NOP_M_IMM21,
EM_PROBE_R_R1_R3_R2,
EM_PROBE_W_R1_R3_R2,
EM_PROBE_R_R1_R3_IMM2,
EM_PROBE_W_R1_R3_IMM2,
EM_PROBE_RW_FAULT_R3_IMM2,
EM_PROBE_R_FAULT_R3_IMM2,
EM_PROBE_W_FAULT_R3_IMM2,
EM_ITC_D_R2,
EM_ITC_I_R2,
EM_MOV_RR_R3_R2,
EM_MOV_DBR_R3_R2,
EM_MOV_IBR_R3_R2,
EM_MOV_PKR_R3_R2,
EM_MOV_PMC_R3_R2,
EM_MOV_PMD_R3_R2,
EM_MOV_MSR_R3_R2,
EM_ITR_D_DTR_R3_R2,
EM_ITR_I_ITR_R3_R2,
EM_MOV_R1_RR_R3,
EM_MOV_R1_DBR_R3,
EM_MOV_R1_IBR_R3,
EM_MOV_R1_PKR_R3,
EM_MOV_R1_PMC_R3,
EM_MOV_R1_MSR_R3,
EM_MOV_R1_PMD_R3,
EM_MOV_R1_CPUID_R3,
EM_SUM_IMM24,
EM_RUM_IMM24,
EM_SSM_IMM24,
EM_RSM_IMM24,
EM_PTC_L_R3_R2,
EM_PTC_G_R3_R2,
EM_PTC_GA_R3_R2,
EM_PTR_D_R3_R2,
EM_PTR_I_R3_R2,
EM_THASH_R1_R3,
EM_TTAG_R1_R3,
EM_TPA_R1_R3,
EM_TAK_R1_R3,
EM_HALT_R3,
EM_BR_COND_SPTK_FEW_TARGET25,
EM_BR_COND_SPTK_MANY_TARGET25,
EM_BR_COND_SPNT_FEW_TARGET25,
EM_BR_COND_SPNT_MANY_TARGET25,
EM_BR_COND_DPTK_FEW_TARGET25,
EM_BR_COND_DPTK_MANY_TARGET25,
EM_BR_COND_DPNT_FEW_TARGET25,
EM_BR_COND_DPNT_MANY_TARGET25,
EM_BR_COND_SPTK_FEW_CLR_TARGET25,
EM_BR_COND_SPTK_MANY_CLR_TARGET25,
EM_BR_COND_SPNT_FEW_CLR_TARGET25,
EM_BR_COND_SPNT_MANY_CLR_TARGET25,
EM_BR_COND_DPTK_FEW_CLR_TARGET25,
EM_BR_COND_DPTK_MANY_CLR_TARGET25,
EM_BR_COND_DPNT_FEW_CLR_TARGET25,
EM_BR_COND_DPNT_MANY_CLR_TARGET25,
EM_BR_WEXIT_SPTK_FEW_TARGET25,
EM_BR_WEXIT_SPTK_MANY_TARGET25,
EM_BR_WEXIT_SPNT_FEW_TARGET25,
EM_BR_WEXIT_SPNT_MANY_TARGET25,
EM_BR_WEXIT_DPTK_FEW_TARGET25,
EM_BR_WEXIT_DPTK_MANY_TARGET25,
EM_BR_WEXIT_DPNT_FEW_TARGET25,
EM_BR_WEXIT_DPNT_MANY_TARGET25,
EM_BR_WEXIT_SPTK_FEW_CLR_TARGET25,
EM_BR_WEXIT_SPTK_MANY_CLR_TARGET25,
EM_BR_WEXIT_SPNT_FEW_CLR_TARGET25,
EM_BR_WEXIT_SPNT_MANY_CLR_TARGET25,
EM_BR_WEXIT_DPTK_FEW_CLR_TARGET25,
EM_BR_WEXIT_DPTK_MANY_CLR_TARGET25,
EM_BR_WEXIT_DPNT_FEW_CLR_TARGET25,
EM_BR_WEXIT_DPNT_MANY_CLR_TARGET25,
EM_BR_WTOP_SPTK_FEW_TARGET25,
EM_BR_WTOP_SPTK_MANY_TARGET25,
EM_BR_WTOP_SPNT_FEW_TARGET25,
EM_BR_WTOP_SPNT_MANY_TARGET25,
EM_BR_WTOP_DPTK_FEW_TARGET25,
EM_BR_WTOP_DPTK_MANY_TARGET25,
EM_BR_WTOP_DPNT_FEW_TARGET25,
EM_BR_WTOP_DPNT_MANY_TARGET25,
EM_BR_WTOP_SPTK_FEW_CLR_TARGET25,
EM_BR_WTOP_SPTK_MANY_CLR_TARGET25,
EM_BR_WTOP_SPNT_FEW_CLR_TARGET25,
EM_BR_WTOP_SPNT_MANY_CLR_TARGET25,
EM_BR_WTOP_DPTK_FEW_CLR_TARGET25,
EM_BR_WTOP_DPTK_MANY_CLR_TARGET25,
EM_BR_WTOP_DPNT_FEW_CLR_TARGET25,
EM_BR_WTOP_DPNT_MANY_CLR_TARGET25,
EM_BR_CLOOP_SPTK_FEW_TARGET25,
EM_BR_CLOOP_SPTK_MANY_TARGET25,
EM_BR_CLOOP_SPNT_FEW_TARGET25,
EM_BR_CLOOP_SPNT_MANY_TARGET25,
EM_BR_CLOOP_DPTK_FEW_TARGET25,
EM_BR_CLOOP_DPTK_MANY_TARGET25,
EM_BR_CLOOP_DPNT_FEW_TARGET25,
EM_BR_CLOOP_DPNT_MANY_TARGET25,
EM_BR_CLOOP_SPTK_FEW_CLR_TARGET25,
EM_BR_CLOOP_SPTK_MANY_CLR_TARGET25,
EM_BR_CLOOP_SPNT_FEW_CLR_TARGET25,
EM_BR_CLOOP_SPNT_MANY_CLR_TARGET25,
EM_BR_CLOOP_DPTK_FEW_CLR_TARGET25,
EM_BR_CLOOP_DPTK_MANY_CLR_TARGET25,
EM_BR_CLOOP_DPNT_FEW_CLR_TARGET25,
EM_BR_CLOOP_DPNT_MANY_CLR_TARGET25,
EM_BR_CEXIT_SPTK_FEW_TARGET25,
EM_BR_CEXIT_SPTK_MANY_TARGET25,
EM_BR_CEXIT_SPNT_FEW_TARGET25,
EM_BR_CEXIT_SPNT_MANY_TARGET25,
EM_BR_CEXIT_DPTK_FEW_TARGET25,
EM_BR_CEXIT_DPTK_MANY_TARGET25,
EM_BR_CEXIT_DPNT_FEW_TARGET25,
EM_BR_CEXIT_DPNT_MANY_TARGET25,
EM_BR_CEXIT_SPTK_FEW_CLR_TARGET25,
EM_BR_CEXIT_SPTK_MANY_CLR_TARGET25,
EM_BR_CEXIT_SPNT_FEW_CLR_TARGET25,
EM_BR_CEXIT_SPNT_MANY_CLR_TARGET25,
EM_BR_CEXIT_DPTK_FEW_CLR_TARGET25,
EM_BR_CEXIT_DPTK_MANY_CLR_TARGET25,
EM_BR_CEXIT_DPNT_FEW_CLR_TARGET25,
EM_BR_CEXIT_DPNT_MANY_CLR_TARGET25,
EM_BR_CTOP_SPTK_FEW_TARGET25,
EM_BR_CTOP_SPTK_MANY_TARGET25,
EM_BR_CTOP_SPNT_FEW_TARGET25,
EM_BR_CTOP_SPNT_MANY_TARGET25,
EM_BR_CTOP_DPTK_FEW_TARGET25,
EM_BR_CTOP_DPTK_MANY_TARGET25,
EM_BR_CTOP_DPNT_FEW_TARGET25,
EM_BR_CTOP_DPNT_MANY_TARGET25,
EM_BR_CTOP_SPTK_FEW_CLR_TARGET25,
EM_BR_CTOP_SPTK_MANY_CLR_TARGET25,
EM_BR_CTOP_SPNT_FEW_CLR_TARGET25,
EM_BR_CTOP_SPNT_MANY_CLR_TARGET25,
EM_BR_CTOP_DPTK_FEW_CLR_TARGET25,
EM_BR_CTOP_DPTK_MANY_CLR_TARGET25,
EM_BR_CTOP_DPNT_FEW_CLR_TARGET25,
EM_BR_CTOP_DPNT_MANY_CLR_TARGET25,
EM_BR_CALL_SPTK_FEW_B1_TARGET25,
EM_BR_CALL_SPTK_MANY_B1_TARGET25,
EM_BR_CALL_SPNT_FEW_B1_TARGET25,
EM_BR_CALL_SPNT_MANY_B1_TARGET25,
EM_BR_CALL_DPTK_FEW_B1_TARGET25,
EM_BR_CALL_DPTK_MANY_B1_TARGET25,
EM_BR_CALL_DPNT_FEW_B1_TARGET25,
EM_BR_CALL_DPNT_MANY_B1_TARGET25,
EM_BR_CALL_SPTK_FEW_CLR_B1_TARGET25,
EM_BR_CALL_SPTK_MANY_CLR_B1_TARGET25,
EM_BR_CALL_SPNT_FEW_CLR_B1_TARGET25,
EM_BR_CALL_SPNT_MANY_CLR_B1_TARGET25,
EM_BR_CALL_DPTK_FEW_CLR_B1_TARGET25,
EM_BR_CALL_DPTK_MANY_CLR_B1_TARGET25,
EM_BR_CALL_DPNT_FEW_CLR_B1_TARGET25,
EM_BR_CALL_DPNT_MANY_CLR_B1_TARGET25,
EM_BR_COND_SPTK_FEW_B2,
EM_BR_COND_SPTK_MANY_B2,
EM_BR_COND_SPNT_FEW_B2,
EM_BR_COND_SPNT_MANY_B2,
EM_BR_COND_DPTK_FEW_B2,
EM_BR_COND_DPTK_MANY_B2,
EM_BR_COND_DPNT_FEW_B2,
EM_BR_COND_DPNT_MANY_B2,
EM_BR_COND_SPTK_FEW_CLR_B2,
EM_BR_COND_SPTK_MANY_CLR_B2,
EM_BR_COND_SPNT_FEW_CLR_B2,
EM_BR_COND_SPNT_MANY_CLR_B2,
EM_BR_COND_DPTK_FEW_CLR_B2,
EM_BR_COND_DPTK_MANY_CLR_B2,
EM_BR_COND_DPNT_FEW_CLR_B2,
EM_BR_COND_DPNT_MANY_CLR_B2,
EM_BR_IA_SPTK_FEW_B2,
EM_BR_IA_SPTK_MANY_B2,
EM_BR_IA_SPNT_FEW_B2,
EM_BR_IA_SPNT_MANY_B2,
EM_BR_IA_DPTK_FEW_B2,
EM_BR_IA_DPTK_MANY_B2,
EM_BR_IA_DPNT_FEW_B2,
EM_BR_IA_DPNT_MANY_B2,
EM_BR_IA_SPTK_FEW_CLR_B2,
EM_BR_IA_SPTK_MANY_CLR_B2,
EM_BR_IA_SPNT_FEW_CLR_B2,
EM_BR_IA_SPNT_MANY_CLR_B2,
EM_BR_IA_DPTK_FEW_CLR_B2,
EM_BR_IA_DPTK_MANY_CLR_B2,
EM_BR_IA_DPNT_FEW_CLR_B2,
EM_BR_IA_DPNT_MANY_CLR_B2,
EM_BR_RET_SPTK_FEW_B2,
EM_BR_RET_SPTK_MANY_B2,
EM_BR_RET_SPNT_FEW_B2,
EM_BR_RET_SPNT_MANY_B2,
EM_BR_RET_DPTK_FEW_B2,
EM_BR_RET_DPTK_MANY_B2,
EM_BR_RET_DPNT_FEW_B2,
EM_BR_RET_DPNT_MANY_B2,
EM_BR_RET_SPTK_FEW_CLR_B2,
EM_BR_RET_SPTK_MANY_CLR_B2,
EM_BR_RET_SPNT_FEW_CLR_B2,
EM_BR_RET_SPNT_MANY_CLR_B2,
EM_BR_RET_DPTK_FEW_CLR_B2,
EM_BR_RET_DPTK_MANY_CLR_B2,
EM_BR_RET_DPNT_FEW_CLR_B2,
EM_BR_RET_DPNT_MANY_CLR_B2,
EM_BR_CALL_SPTK_FEW_B1_B2,
EM_BR_CALL_SPTK_MANY_B1_B2,
EM_BR_CALL_SPNT_FEW_B1_B2,
EM_BR_CALL_SPNT_MANY_B1_B2,
EM_BR_CALL_DPTK_FEW_B1_B2,
EM_BR_CALL_DPTK_MANY_B1_B2,
EM_BR_CALL_DPNT_FEW_B1_B2,
EM_BR_CALL_DPNT_MANY_B1_B2,
EM_BR_CALL_SPTK_FEW_CLR_B1_B2,
EM_BR_CALL_SPTK_MANY_CLR_B1_B2,
EM_BR_CALL_SPNT_FEW_CLR_B1_B2,
EM_BR_CALL_SPNT_MANY_CLR_B1_B2,
EM_BR_CALL_DPTK_FEW_CLR_B1_B2,
EM_BR_CALL_DPTK_MANY_CLR_B1_B2,
EM_BR_CALL_DPNT_FEW_CLR_B1_B2,
EM_BR_CALL_DPNT_MANY_CLR_B1_B2,
EM_BRP_SPTK_TARGET25_TAG13,
EM_BRP_SPTK_IMP_TARGET25_TAG13,
EM_BRP_LOOP_TARGET25_TAG13,
EM_BRP_LOOP_IMP_TARGET25_TAG13,
EM_BRP_DPTK_TARGET25_TAG13,
EM_BRP_DPTK_IMP_TARGET25_TAG13,
EM_BRP_EXIT_TARGET25_TAG13,
EM_BRP_EXIT_IMP_TARGET25_TAG13,
EM_BRP_SPTK_B2_TAG13,
EM_BRP_SPTK_IMP_B2_TAG13,
EM_BRP_DPTK_B2_TAG13,
EM_BRP_DPTK_IMP_B2_TAG13,
EM_BRP_RET_SPTK_B2_TAG13,
EM_BRP_RET_SPTK_IMP_B2_TAG13,
EM_BRP_RET_DPTK_B2_TAG13,
EM_BRP_RET_DPTK_IMP_B2_TAG13,
EM_COVER,
EM_CLRRRB,
EM_CLRRRB_PR,
EM_RFI,
EM_RFI_X,
EM_BSW_0,
EM_BSW_1,
EM_EPC,
EM_BREAK_B_IMM21,
EM_NOP_B_IMM21,
EM_FMA_S0_F1_F3_F4_F2,
EM_FMA_S1_F1_F3_F4_F2,
EM_FMA_S2_F1_F3_F4_F2,
EM_FMA_S3_F1_F3_F4_F2,
EM_FMA_S_S0_F1_F3_F4_F2,
EM_FMA_S_S1_F1_F3_F4_F2,
EM_FMA_S_S2_F1_F3_F4_F2,
EM_FMA_S_S3_F1_F3_F4_F2,
EM_FMA_D_S0_F1_F3_F4_F2,
EM_FMA_D_S1_F1_F3_F4_F2,
EM_FMA_D_S2_F1_F3_F4_F2,
EM_FMA_D_S3_F1_F3_F4_F2,
EM_FPMA_S0_F1_F3_F4_F2,
EM_FPMA_S1_F1_F3_F4_F2,
EM_FPMA_S2_F1_F3_F4_F2,
EM_FPMA_S3_F1_F3_F4_F2,
EM_FMS_S0_F1_F3_F4_F2,
EM_FMS_S1_F1_F3_F4_F2,
EM_FMS_S2_F1_F3_F4_F2,
EM_FMS_S3_F1_F3_F4_F2,
EM_FMS_S_S0_F1_F3_F4_F2,
EM_FMS_S_S1_F1_F3_F4_F2,
EM_FMS_S_S2_F1_F3_F4_F2,
EM_FMS_S_S3_F1_F3_F4_F2,
EM_FMS_D_S0_F1_F3_F4_F2,
EM_FMS_D_S1_F1_F3_F4_F2,
EM_FMS_D_S2_F1_F3_F4_F2,
EM_FMS_D_S3_F1_F3_F4_F2,
EM_FPMS_S0_F1_F3_F4_F2,
EM_FPMS_S1_F1_F3_F4_F2,
EM_FPMS_S2_F1_F3_F4_F2,
EM_FPMS_S3_F1_F3_F4_F2,
EM_FNMA_S0_F1_F3_F4_F2,
EM_FNMA_S1_F1_F3_F4_F2,
EM_FNMA_S2_F1_F3_F4_F2,
EM_FNMA_S3_F1_F3_F4_F2,
EM_FNMA_S_S0_F1_F3_F4_F2,
EM_FNMA_S_S1_F1_F3_F4_F2,
EM_FNMA_S_S2_F1_F3_F4_F2,
EM_FNMA_S_S3_F1_F3_F4_F2,
EM_FNMA_D_S0_F1_F3_F4_F2,
EM_FNMA_D_S1_F1_F3_F4_F2,
EM_FNMA_D_S2_F1_F3_F4_F2,
EM_FNMA_D_S3_F1_F3_F4_F2,
EM_FPNMA_S0_F1_F3_F4_F2,
EM_FPNMA_S1_F1_F3_F4_F2,
EM_FPNMA_S2_F1_F3_F4_F2,
EM_FPNMA_S3_F1_F3_F4_F2,
EM_XMA_L_F1_F3_F4_F2,
EM_XMA_H_F1_F3_F4_F2,
EM_XMA_HU_F1_F3_F4_F2,
EM_FSELECT_F1_F3_F4_F2,
EM_FCMP_EQ_S0_P1_P2_F2_F3,
EM_FCMP_EQ_S1_P1_P2_F2_F3,
EM_FCMP_EQ_S2_P1_P2_F2_F3,
EM_FCMP_EQ_S3_P1_P2_F2_F3,
EM_FCMP_LT_S0_P1_P2_F2_F3,
EM_FCMP_LT_S1_P1_P2_F2_F3,
EM_FCMP_LT_S2_P1_P2_F2_F3,
EM_FCMP_LT_S3_P1_P2_F2_F3,
EM_FCMP_LE_S0_P1_P2_F2_F3,
EM_FCMP_LE_S1_P1_P2_F2_F3,
EM_FCMP_LE_S2_P1_P2_F2_F3,
EM_FCMP_LE_S3_P1_P2_F2_F3,
EM_FCMP_UNORD_S0_P1_P2_F2_F3,
EM_FCMP_UNORD_S1_P1_P2_F2_F3,
EM_FCMP_UNORD_S2_P1_P2_F2_F3,
EM_FCMP_UNORD_S3_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S0_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S1_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S2_P1_P2_F2_F3,
EM_FCMP_EQ_UNC_S3_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S0_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S1_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S2_P1_P2_F2_F3,
EM_FCMP_LT_UNC_S3_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S0_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S1_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S2_P1_P2_F2_F3,
EM_FCMP_LE_UNC_S3_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S0_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S1_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S2_P1_P2_F2_F3,
EM_FCMP_UNORD_UNC_S3_P1_P2_F2_F3,
EM_FCLASS_M_P1_P2_F2_FCLASS9,
EM_FCLASS_M_UNC_P1_P2_F2_FCLASS9,
EM_FRCPA_S0_F1_P2_F2_F3,
EM_FRCPA_S1_F1_P2_F2_F3,
EM_FRCPA_S2_F1_P2_F2_F3,
EM_FRCPA_S3_F1_P2_F2_F3,
EM_FPRCPA_S0_F1_P2_F2_F3,
EM_FPRCPA_S1_F1_P2_F2_F3,
EM_FPRCPA_S2_F1_P2_F2_F3,
EM_FPRCPA_S3_F1_P2_F2_F3,
EM_FRSQRTA_S0_F1_P2_F3,
EM_FRSQRTA_S1_F1_P2_F3,
EM_FRSQRTA_S2_F1_P2_F3,
EM_FRSQRTA_S3_F1_P2_F3,
EM_FPRSQRTA_S0_F1_P2_F3,
EM_FPRSQRTA_S1_F1_P2_F3,
EM_FPRSQRTA_S2_F1_P2_F3,
EM_FPRSQRTA_S3_F1_P2_F3,
EM_FMIN_S0_F1_F2_F3,
EM_FMIN_S1_F1_F2_F3,
EM_FMIN_S2_F1_F2_F3,
EM_FMIN_S3_F1_F2_F3,
EM_FMAX_S0_F1_F2_F3,
EM_FMAX_S1_F1_F2_F3,
EM_FMAX_S2_F1_F2_F3,
EM_FMAX_S3_F1_F2_F3,
EM_FAMIN_S0_F1_F2_F3,
EM_FAMIN_S1_F1_F2_F3,
EM_FAMIN_S2_F1_F2_F3,
EM_FAMIN_S3_F1_F2_F3,
EM_FAMAX_S0_F1_F2_F3,
EM_FAMAX_S1_F1_F2_F3,
EM_FAMAX_S2_F1_F2_F3,
EM_FAMAX_S3_F1_F2_F3,
EM_FPMIN_S0_F1_F2_F3,
EM_FPMIN_S1_F1_F2_F3,
EM_FPMIN_S2_F1_F2_F3,
EM_FPMIN_S3_F1_F2_F3,
EM_FPMAX_S0_F1_F2_F3,
EM_FPMAX_S1_F1_F2_F3,
EM_FPMAX_S2_F1_F2_F3,
EM_FPMAX_S3_F1_F2_F3,
EM_FPAMIN_S0_F1_F2_F3,
EM_FPAMIN_S1_F1_F2_F3,
EM_FPAMIN_S2_F1_F2_F3,
EM_FPAMIN_S3_F1_F2_F3,
EM_FPAMAX_S0_F1_F2_F3,
EM_FPAMAX_S1_F1_F2_F3,
EM_FPAMAX_S2_F1_F2_F3,
EM_FPAMAX_S3_F1_F2_F3,
EM_FPCMP_EQ_S0_F1_F2_F3,
EM_FPCMP_EQ_S1_F1_F2_F3,
EM_FPCMP_EQ_S2_F1_F2_F3,
EM_FPCMP_EQ_S3_F1_F2_F3,
EM_FPCMP_LT_S0_F1_F2_F3,
EM_FPCMP_LT_S1_F1_F2_F3,
EM_FPCMP_LT_S2_F1_F2_F3,
EM_FPCMP_LT_S3_F1_F2_F3,
EM_FPCMP_LE_S0_F1_F2_F3,
EM_FPCMP_LE_S1_F1_F2_F3,
EM_FPCMP_LE_S2_F1_F2_F3,
EM_FPCMP_LE_S3_F1_F2_F3,
EM_FPCMP_UNORD_S0_F1_F2_F3,
EM_FPCMP_UNORD_S1_F1_F2_F3,
EM_FPCMP_UNORD_S2_F1_F2_F3,
EM_FPCMP_UNORD_S3_F1_F2_F3,
EM_FPCMP_NEQ_S0_F1_F2_F3,
EM_FPCMP_NEQ_S1_F1_F2_F3,
EM_FPCMP_NEQ_S2_F1_F2_F3,
EM_FPCMP_NEQ_S3_F1_F2_F3,
EM_FPCMP_NLT_S0_F1_F2_F3,
EM_FPCMP_NLT_S1_F1_F2_F3,
EM_FPCMP_NLT_S2_F1_F2_F3,
EM_FPCMP_NLT_S3_F1_F2_F3,
EM_FPCMP_NLE_S0_F1_F2_F3,
EM_FPCMP_NLE_S1_F1_F2_F3,
EM_FPCMP_NLE_S2_F1_F2_F3,
EM_FPCMP_NLE_S3_F1_F2_F3,
EM_FPCMP_ORD_S0_F1_F2_F3,
EM_FPCMP_ORD_S1_F1_F2_F3,
EM_FPCMP_ORD_S2_F1_F2_F3,
EM_FPCMP_ORD_S3_F1_F2_F3,
EM_FMERGE_S_F1_F2_F3,
EM_FMERGE_NS_F1_F2_F3,
EM_FMERGE_SE_F1_F2_F3,
EM_FMIX_LR_F1_F2_F3,
EM_FMIX_R_F1_F2_F3,
EM_FMIX_L_F1_F2_F3,
EM_FSXT_R_F1_F2_F3,
EM_FSXT_L_F1_F2_F3,
EM_FPACK_F1_F2_F3,
EM_FSWAP_F1_F2_F3,
EM_FSWAP_NL_F1_F2_F3,
EM_FSWAP_NR_F1_F2_F3,
EM_FAND_F1_F2_F3,
EM_FANDCM_F1_F2_F3,
EM_FOR_F1_F2_F3,
EM_FXOR_F1_F2_F3,
EM_FPMERGE_S_F1_F2_F3,
EM_FPMERGE_NS_F1_F2_F3,
EM_FPMERGE_SE_F1_F2_F3,
EM_FCVT_FX_S0_F1_F2,
EM_FCVT_FX_S1_F1_F2,
EM_FCVT_FX_S2_F1_F2,
EM_FCVT_FX_S3_F1_F2,
EM_FCVT_FXU_S0_F1_F2,
EM_FCVT_FXU_S1_F1_F2,
EM_FCVT_FXU_S2_F1_F2,
EM_FCVT_FXU_S3_F1_F2,
EM_FCVT_FX_TRUNC_S0_F1_F2,
EM_FCVT_FX_TRUNC_S1_F1_F2,
EM_FCVT_FX_TRUNC_S2_F1_F2,
EM_FCVT_FX_TRUNC_S3_F1_F2,
EM_FCVT_FXU_TRUNC_S0_F1_F2,
EM_FCVT_FXU_TRUNC_S1_F1_F2,
EM_FCVT_FXU_TRUNC_S2_F1_F2,
EM_FCVT_FXU_TRUNC_S3_F1_F2,
EM_FPCVT_FX_S0_F1_F2,
EM_FPCVT_FX_S1_F1_F2,
EM_FPCVT_FX_S2_F1_F2,
EM_FPCVT_FX_S3_F1_F2,
EM_FPCVT_FXU_S0_F1_F2,
EM_FPCVT_FXU_S1_F1_F2,
EM_FPCVT_FXU_S2_F1_F2,
EM_FPCVT_FXU_S3_F1_F2,
EM_FPCVT_FX_TRUNC_S0_F1_F2,
EM_FPCVT_FX_TRUNC_S1_F1_F2,
EM_FPCVT_FX_TRUNC_S2_F1_F2,
EM_FPCVT_FX_TRUNC_S3_F1_F2,
EM_FPCVT_FXU_TRUNC_S0_F1_F2,
EM_FPCVT_FXU_TRUNC_S1_F1_F2,
EM_FPCVT_FXU_TRUNC_S2_F1_F2,
EM_FPCVT_FXU_TRUNC_S3_F1_F2,
EM_FCVT_XF_F1_F2,
EM_FSETC_S0_AMASK7_OMASK7,
EM_FSETC_S1_AMASK7_OMASK7,
EM_FSETC_S2_AMASK7_OMASK7,
EM_FSETC_S3_AMASK7_OMASK7,
EM_FCLRF_S0,
EM_FCLRF_S1,
EM_FCLRF_S2,
EM_FCLRF_S3,
EM_FCHKF_S0_TARGET25,
EM_FCHKF_S1_TARGET25,
EM_FCHKF_S2_TARGET25,
EM_FCHKF_S3_TARGET25,
EM_BREAK_F_IMM21,
EM_NOP_F_IMM21,
EM_BREAK_X_IMM62,
EM_NOP_X_IMM62,
EM_MOVL_R1_IMM64,
EM_BRL_COND_SPTK_FEW_TARGET64,
EM_BRL_COND_SPTK_MANY_TARGET64,
EM_BRL_COND_SPNT_FEW_TARGET64,
EM_BRL_COND_SPNT_MANY_TARGET64,
EM_BRL_COND_DPTK_FEW_TARGET64,
EM_BRL_COND_DPTK_MANY_TARGET64,
EM_BRL_COND_DPNT_FEW_TARGET64,
EM_BRL_COND_DPNT_MANY_TARGET64,
EM_BRL_COND_SPTK_FEW_CLR_TARGET64,
EM_BRL_COND_SPTK_MANY_CLR_TARGET64,
EM_BRL_COND_SPNT_FEW_CLR_TARGET64,
EM_BRL_COND_SPNT_MANY_CLR_TARGET64,
EM_BRL_COND_DPTK_FEW_CLR_TARGET64,
EM_BRL_COND_DPTK_MANY_CLR_TARGET64,
EM_BRL_COND_DPNT_FEW_CLR_TARGET64,
EM_BRL_COND_DPNT_MANY_CLR_TARGET64,
EM_BRL_CALL_SPTK_FEW_B1_TARGET64,
EM_BRL_CALL_SPTK_MANY_B1_TARGET64,
EM_BRL_CALL_SPNT_FEW_B1_TARGET64,
EM_BRL_CALL_SPNT_MANY_B1_TARGET64,
EM_BRL_CALL_DPTK_FEW_B1_TARGET64,
EM_BRL_CALL_DPTK_MANY_B1_TARGET64,
EM_BRL_CALL_DPNT_FEW_B1_TARGET64,
EM_BRL_CALL_DPNT_MANY_B1_TARGET64,
EM_BRL_CALL_SPTK_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_SPTK_MANY_CLR_B1_TARGET64,
EM_BRL_CALL_SPNT_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_SPNT_MANY_CLR_B1_TARGET64,
EM_BRL_CALL_DPTK_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_DPTK_MANY_CLR_B1_TARGET64,
EM_BRL_CALL_DPNT_FEW_CLR_B1_TARGET64,
EM_BRL_CALL_DPNT_MANY_CLR_B1_TARGET64,
EM_INST_LAST
} Inst_id_t2;

#endif

#endif /* _INST_ID_H */

typedef Inst_id_t EM_Decoder_Inst_Id;


/* ----------  Definition of IPF resources  ---------- */

#ifndef EM_H

typedef enum
{
    EM_AR_KR0  = 0,
    EM_AR_KR1  = 1,
    EM_AR_KR2  = 2,
    EM_AR_KR3  = 3,
    EM_AR_KR4  = 4,
    EM_AR_KR5  = 5,
    EM_AR_KR6  = 6,
    EM_AR_KR7  = 7,
    /* ar8-15 reserved */
    EM_AR_RSC  = 16,
    EM_AR_BSP  = 17,
    EM_AR_BSPSTORE = 18,
    EM_AR_RNAT = 19,
    /* ar20 reserved */
    EM_AR_FCR  = 21, 
    /* ar22-23 reserved */
    EM_AR_EFLAG  = 24,
    EM_AR_CSD    = 25,
    EM_AR_SSD    = 26,
    EM_AR_CFLG   = 27,
    EM_AR_FSR    = 28,
    EM_AR_FIR    = 29,
    EM_AR_FDR    = 30,
    /* ar31 reserved */
    EM_AR_CCV    = 32,
    /* ar33-35 reserved */
    EM_AR_UNAT = 36,
    /* ar37-39 reserved */
    EM_AR_FPSR = 40,
    /* ar41-43 reserved */
    EM_AR_ITC  = 44,
    /* ar45-47 reserved */
    /* ar48-63 ignored */
    EM_AR_PFS  = 64,
    EM_AR_LC   = 65,
    EM_AR_EC   = 66,
    /* ar67-111 reserved */
    /* ar112-128 ignored */
    EM_AR_LAST = 128
} EM_areg_num_t;


typedef enum
{
    EM_CR_DCR  = 0,
    EM_CR_ITM  = 1,
    EM_CR_IVA  = 2,
    /*** 3-7 reserved ***/
    EM_CR_PTA  = 8,
    EM_CR_GPTA = 9,
    /*** 10-15 reserved ***/
    EM_CR_IPSR = 16,
    EM_CR_ISR  = 17,
    /*** 18 reserved ***/
    EM_CR_IIP  = 19,
    EM_CR_IFA  = 20,
    EM_CR_ITIR = 21,
    EM_CR_IIPA = 22,
    EM_CR_IFS  = 23,
    EM_CR_IIM  = 24,
    EM_CR_IHA  = 25,
    /*** 25-63 reserved ***/
    /*** SAPIC registers ***/
    EM_CR_LID  = 64,
    EM_CR_IVR  = 65,
    EM_CR_TPR  = 66,
    EM_CR_EOI  = 67,
    EM_CR_IRR0 = 68,
    EM_CR_IRR1 = 69,
    EM_CR_IRR2 = 70,
    EM_CR_IRR3 = 71,
    EM_CR_ITV  = 72,
    EM_CR_PMV  = 73,
    EM_CR_CMCV = 74,
    /*** 75-79 reserved  ***/
    EM_CR_LRR0 = 80,
    EM_CR_LRR1 = 81,
    /*** 82-127 reserved ***/
    EM_CR_LAST = 128
} EM_creg_num_t;


#endif /* EM_H */

#ifndef _IPF_RESOURCE_LIST_H_

typedef enum {
    IPF_RESOURCE_NONE = 0,
    IPF_RESOURCE_GR0,      
    IPF_RESOURCE_GR1,
    IPF_RESOURCE_GR2,
    IPF_RESOURCE_GR3,
    IPF_RESOURCE_GR4,
    IPF_RESOURCE_GR5,
    IPF_RESOURCE_GR6,
    IPF_RESOURCE_GR7,
    IPF_RESOURCE_GR8,
    IPF_RESOURCE_GR9,
    IPF_RESOURCE_GR10,
    IPF_RESOURCE_GR11,
    IPF_RESOURCE_GR12,
    IPF_RESOURCE_GR13,
    IPF_RESOURCE_GR14,
    IPF_RESOURCE_GR15,
    IPF_RESOURCE_GR16,
    IPF_RESOURCE_GR17,
    IPF_RESOURCE_GR18,
    IPF_RESOURCE_GR19,
    IPF_RESOURCE_GR20,
    IPF_RESOURCE_GR21,
    IPF_RESOURCE_GR22,
    IPF_RESOURCE_GR23,
    IPF_RESOURCE_GR24,
    IPF_RESOURCE_GR25,
    IPF_RESOURCE_GR26,
    IPF_RESOURCE_GR27,
    IPF_RESOURCE_GR28,
    IPF_RESOURCE_GR29,
    IPF_RESOURCE_GR30,
    IPF_RESOURCE_GR31,
    IPF_RESOURCE_GR32,
    IPF_RESOURCE_GR33,
    IPF_RESOURCE_GR34,
    IPF_RESOURCE_GR35,
    IPF_RESOURCE_GR36,
    IPF_RESOURCE_GR37,
    IPF_RESOURCE_GR38,
    IPF_RESOURCE_GR39,
    IPF_RESOURCE_GR40,
    IPF_RESOURCE_GR41,
    IPF_RESOURCE_GR42,
    IPF_RESOURCE_GR43,
    IPF_RESOURCE_GR44,
    IPF_RESOURCE_GR45,
    IPF_RESOURCE_GR46,
    IPF_RESOURCE_GR47,
    IPF_RESOURCE_GR48,
    IPF_RESOURCE_GR49,
    IPF_RESOURCE_GR50,
    IPF_RESOURCE_GR51,
    IPF_RESOURCE_GR52,
    IPF_RESOURCE_GR53,
    IPF_RESOURCE_GR54,
    IPF_RESOURCE_GR55,
    IPF_RESOURCE_GR56,
    IPF_RESOURCE_GR57,
    IPF_RESOURCE_GR58,
    IPF_RESOURCE_GR59,
    IPF_RESOURCE_GR60,
    IPF_RESOURCE_GR61,
    IPF_RESOURCE_GR62,
    IPF_RESOURCE_GR63,
    IPF_RESOURCE_GR64,
    IPF_RESOURCE_GR65,
    IPF_RESOURCE_GR66,
    IPF_RESOURCE_GR67,
    IPF_RESOURCE_GR68,
    IPF_RESOURCE_GR69,
    IPF_RESOURCE_GR70,
    IPF_RESOURCE_GR71,
    IPF_RESOURCE_GR72,
    IPF_RESOURCE_GR73,
    IPF_RESOURCE_GR74,
    IPF_RESOURCE_GR75,
    IPF_RESOURCE_GR76,
    IPF_RESOURCE_GR77,
    IPF_RESOURCE_GR78,
    IPF_RESOURCE_GR79,
    IPF_RESOURCE_GR80,
    IPF_RESOURCE_GR81,
    IPF_RESOURCE_GR82,
    IPF_RESOURCE_GR83,
    IPF_RESOURCE_GR84,
    IPF_RESOURCE_GR85,
    IPF_RESOURCE_GR86,
    IPF_RESOURCE_GR87,
    IPF_RESOURCE_GR88,
    IPF_RESOURCE_GR89,
    IPF_RESOURCE_GR90,
    IPF_RESOURCE_GR91,
    IPF_RESOURCE_GR92,
    IPF_RESOURCE_GR93,
    IPF_RESOURCE_GR94,
    IPF_RESOURCE_GR95,
    IPF_RESOURCE_GR96,
    IPF_RESOURCE_GR97,
    IPF_RESOURCE_GR98,
    IPF_RESOURCE_GR99,
    IPF_RESOURCE_GR100,
    IPF_RESOURCE_GR101,
    IPF_RESOURCE_GR102,
    IPF_RESOURCE_GR103,
    IPF_RESOURCE_GR104,
    IPF_RESOURCE_GR105,
    IPF_RESOURCE_GR106,
    IPF_RESOURCE_GR107,
    IPF_RESOURCE_GR108,
    IPF_RESOURCE_GR109,
    IPF_RESOURCE_GR110,
    IPF_RESOURCE_GR111,
    IPF_RESOURCE_GR112,
    IPF_RESOURCE_GR113,
    IPF_RESOURCE_GR114,
    IPF_RESOURCE_GR115,
    IPF_RESOURCE_GR116,
    IPF_RESOURCE_GR117,
    IPF_RESOURCE_GR118,
    IPF_RESOURCE_GR119,
    IPF_RESOURCE_GR120,
    IPF_RESOURCE_GR121,
    IPF_RESOURCE_GR122,
    IPF_RESOURCE_GR123,
    IPF_RESOURCE_GR124,
    IPF_RESOURCE_GR125,
    IPF_RESOURCE_GR126,
    IPF_RESOURCE_GR127,
    IPF_RESOURCE_FR0,   
    IPF_RESOURCE_FR1,   
    IPF_RESOURCE_FR2,
    IPF_RESOURCE_FR3,
    IPF_RESOURCE_FR4,
    IPF_RESOURCE_FR5,
    IPF_RESOURCE_FR6,
    IPF_RESOURCE_FR7,
    IPF_RESOURCE_FR8,
    IPF_RESOURCE_FR9,
    IPF_RESOURCE_FR10,
    IPF_RESOURCE_FR11,
    IPF_RESOURCE_FR12,
    IPF_RESOURCE_FR13,
    IPF_RESOURCE_FR14,
    IPF_RESOURCE_FR15,
    IPF_RESOURCE_FR16,
    IPF_RESOURCE_FR17,
    IPF_RESOURCE_FR18,
    IPF_RESOURCE_FR19,
    IPF_RESOURCE_FR20,
    IPF_RESOURCE_FR21,
    IPF_RESOURCE_FR22,
    IPF_RESOURCE_FR23,
    IPF_RESOURCE_FR24,
    IPF_RESOURCE_FR25,
    IPF_RESOURCE_FR26,
    IPF_RESOURCE_FR27,
    IPF_RESOURCE_FR28,
    IPF_RESOURCE_FR29,
    IPF_RESOURCE_FR30,
    IPF_RESOURCE_FR31,
    IPF_RESOURCE_FR32,
    IPF_RESOURCE_FR33,
    IPF_RESOURCE_FR34,
    IPF_RESOURCE_FR35,
    IPF_RESOURCE_FR36,
    IPF_RESOURCE_FR37,
    IPF_RESOURCE_FR38,
    IPF_RESOURCE_FR39,
    IPF_RESOURCE_FR40,
    IPF_RESOURCE_FR41,
    IPF_RESOURCE_FR42,
    IPF_RESOURCE_FR43,
    IPF_RESOURCE_FR44,
    IPF_RESOURCE_FR45,
    IPF_RESOURCE_FR46,
    IPF_RESOURCE_FR47,
    IPF_RESOURCE_FR48,
    IPF_RESOURCE_FR49,
    IPF_RESOURCE_FR50,
    IPF_RESOURCE_FR51,
    IPF_RESOURCE_FR52,
    IPF_RESOURCE_FR53,
    IPF_RESOURCE_FR54,
    IPF_RESOURCE_FR55,
    IPF_RESOURCE_FR56,
    IPF_RESOURCE_FR57,
    IPF_RESOURCE_FR58,
    IPF_RESOURCE_FR59,
    IPF_RESOURCE_FR60,
    IPF_RESOURCE_FR61,
    IPF_RESOURCE_FR62,
    IPF_RESOURCE_FR63,
    IPF_RESOURCE_FR64,
    IPF_RESOURCE_FR65,
    IPF_RESOURCE_FR66,
    IPF_RESOURCE_FR67,
    IPF_RESOURCE_FR68,
    IPF_RESOURCE_FR69,
    IPF_RESOURCE_FR70,
    IPF_RESOURCE_FR71,
    IPF_RESOURCE_FR72,
    IPF_RESOURCE_FR73,
    IPF_RESOURCE_FR74,
    IPF_RESOURCE_FR75,
    IPF_RESOURCE_FR76,
    IPF_RESOURCE_FR77,
    IPF_RESOURCE_FR78,
    IPF_RESOURCE_FR79,
    IPF_RESOURCE_FR80,
    IPF_RESOURCE_FR81,
    IPF_RESOURCE_FR82,
    IPF_RESOURCE_FR83,
    IPF_RESOURCE_FR84,
    IPF_RESOURCE_FR85,
    IPF_RESOURCE_FR86,
    IPF_RESOURCE_FR87,
    IPF_RESOURCE_FR88,
    IPF_RESOURCE_FR89,
    IPF_RESOURCE_FR90,
    IPF_RESOURCE_FR91,
    IPF_RESOURCE_FR92,
    IPF_RESOURCE_FR93,
    IPF_RESOURCE_FR94,
    IPF_RESOURCE_FR95,
    IPF_RESOURCE_FR96,
    IPF_RESOURCE_FR97,
    IPF_RESOURCE_FR98,
    IPF_RESOURCE_FR99,
    IPF_RESOURCE_FR100,
    IPF_RESOURCE_FR101,
    IPF_RESOURCE_FR102,
    IPF_RESOURCE_FR103,
    IPF_RESOURCE_FR104,
    IPF_RESOURCE_FR105,
    IPF_RESOURCE_FR106,
    IPF_RESOURCE_FR107,
    IPF_RESOURCE_FR108,
    IPF_RESOURCE_FR109,
    IPF_RESOURCE_FR110,
    IPF_RESOURCE_FR111,
    IPF_RESOURCE_FR112,
    IPF_RESOURCE_FR113,
    IPF_RESOURCE_FR114,
    IPF_RESOURCE_FR115,
    IPF_RESOURCE_FR116,
    IPF_RESOURCE_FR117,
    IPF_RESOURCE_FR118,
    IPF_RESOURCE_FR119,
    IPF_RESOURCE_FR120,
    IPF_RESOURCE_FR121,
    IPF_RESOURCE_FR122,
    IPF_RESOURCE_FR123,
    IPF_RESOURCE_FR124,
    IPF_RESOURCE_FR125,
    IPF_RESOURCE_FR126,
    IPF_RESOURCE_FR127,
    IPF_RESOURCE_AR0,
    IPF_RESOURCE_AR1,
    IPF_RESOURCE_AR2,
    IPF_RESOURCE_AR3,
    IPF_RESOURCE_AR4,
    IPF_RESOURCE_AR5,
    IPF_RESOURCE_AR6,
    IPF_RESOURCE_AR7,
    IPF_RESOURCE_AR8,
    IPF_RESOURCE_AR9,
    IPF_RESOURCE_AR10,
    IPF_RESOURCE_AR11,
    IPF_RESOURCE_AR12,
    IPF_RESOURCE_AR13,
    IPF_RESOURCE_AR14,
    IPF_RESOURCE_AR15,
    IPF_RESOURCE_AR16,
    IPF_RESOURCE_AR17,
    IPF_RESOURCE_AR18,
    IPF_RESOURCE_AR19,
    IPF_RESOURCE_AR20,
    IPF_RESOURCE_AR21,
    IPF_RESOURCE_AR22,
    IPF_RESOURCE_AR23,
    IPF_RESOURCE_AR24,
    IPF_RESOURCE_AR25,
    IPF_RESOURCE_AR26,
    IPF_RESOURCE_AR27,
    IPF_RESOURCE_AR28,
    IPF_RESOURCE_AR29,
    IPF_RESOURCE_AR30,
    IPF_RESOURCE_AR31,
    IPF_RESOURCE_AR32,
    IPF_RESOURCE_AR33,
    IPF_RESOURCE_AR34,
    IPF_RESOURCE_AR35,
    IPF_RESOURCE_AR36,
    IPF_RESOURCE_AR37,
    IPF_RESOURCE_AR38,
    IPF_RESOURCE_AR39,
    IPF_RESOURCE_AR40,
    IPF_RESOURCE_AR41,
    IPF_RESOURCE_AR42,
    IPF_RESOURCE_AR43,
    IPF_RESOURCE_AR44,
    IPF_RESOURCE_AR45,
    IPF_RESOURCE_AR46,
    IPF_RESOURCE_AR47,
    IPF_RESOURCE_AR48,
    IPF_RESOURCE_AR49,
    IPF_RESOURCE_AR50,
    IPF_RESOURCE_AR51,
    IPF_RESOURCE_AR52,
    IPF_RESOURCE_AR53,
    IPF_RESOURCE_AR54,
    IPF_RESOURCE_AR55,
    IPF_RESOURCE_AR56,
    IPF_RESOURCE_AR57,
    IPF_RESOURCE_AR58,
    IPF_RESOURCE_AR59,
    IPF_RESOURCE_AR60,
    IPF_RESOURCE_AR61,
    IPF_RESOURCE_AR62,
    IPF_RESOURCE_AR63,
    IPF_RESOURCE_AR64,
    IPF_RESOURCE_AR65,
    IPF_RESOURCE_AR66,
    IPF_RESOURCE_AR67,
    IPF_RESOURCE_AR68,
    IPF_RESOURCE_AR69,
    IPF_RESOURCE_AR70,
    IPF_RESOURCE_AR71,
    IPF_RESOURCE_AR72,
    IPF_RESOURCE_AR73,
    IPF_RESOURCE_AR74,
    IPF_RESOURCE_AR75,
    IPF_RESOURCE_AR76,
    IPF_RESOURCE_AR77,
    IPF_RESOURCE_AR78,
    IPF_RESOURCE_AR79,
    IPF_RESOURCE_AR80,
    IPF_RESOURCE_AR81,
    IPF_RESOURCE_AR82,
    IPF_RESOURCE_AR83,
    IPF_RESOURCE_AR84,
    IPF_RESOURCE_AR85,
    IPF_RESOURCE_AR86,
    IPF_RESOURCE_AR87,
    IPF_RESOURCE_AR88,
    IPF_RESOURCE_AR89,
    IPF_RESOURCE_AR90,
    IPF_RESOURCE_AR91,
    IPF_RESOURCE_AR92,
    IPF_RESOURCE_AR93,
    IPF_RESOURCE_AR94,
    IPF_RESOURCE_AR95,
    IPF_RESOURCE_AR96,
    IPF_RESOURCE_AR97,
    IPF_RESOURCE_AR98,
    IPF_RESOURCE_AR99,
    IPF_RESOURCE_AR100,
    IPF_RESOURCE_AR101,
    IPF_RESOURCE_AR102,
    IPF_RESOURCE_AR103,
    IPF_RESOURCE_AR104,
    IPF_RESOURCE_AR105,
    IPF_RESOURCE_AR106,
    IPF_RESOURCE_AR107,
    IPF_RESOURCE_AR108,
    IPF_RESOURCE_AR109,
    IPF_RESOURCE_AR110,
    IPF_RESOURCE_AR111,
    IPF_RESOURCE_AR112,
    IPF_RESOURCE_AR113,
    IPF_RESOURCE_AR114,
    IPF_RESOURCE_AR115,
    IPF_RESOURCE_AR116,
    IPF_RESOURCE_AR117,
    IPF_RESOURCE_AR118,
    IPF_RESOURCE_AR119,
    IPF_RESOURCE_AR120,
    IPF_RESOURCE_AR121,
    IPF_RESOURCE_AR122,
    IPF_RESOURCE_AR123,
    IPF_RESOURCE_AR124,
    IPF_RESOURCE_AR125,
    IPF_RESOURCE_AR126,
    IPF_RESOURCE_AR127,
    IPF_RESOURCE_PR0,       
    IPF_RESOURCE_PR1,
    IPF_RESOURCE_PR2,
    IPF_RESOURCE_PR3,
    IPF_RESOURCE_PR4,
    IPF_RESOURCE_PR5,
    IPF_RESOURCE_PR6,
    IPF_RESOURCE_PR7,
    IPF_RESOURCE_PR8,
    IPF_RESOURCE_PR9,
    IPF_RESOURCE_PR10,
    IPF_RESOURCE_PR11,
    IPF_RESOURCE_PR12,
    IPF_RESOURCE_PR13,
    IPF_RESOURCE_PR14,
    IPF_RESOURCE_PR15,
    IPF_RESOURCE_PR16,
    IPF_RESOURCE_PR17,
    IPF_RESOURCE_PR18,
    IPF_RESOURCE_PR19,
    IPF_RESOURCE_PR20,
    IPF_RESOURCE_PR21,
    IPF_RESOURCE_PR22,
    IPF_RESOURCE_PR23,
    IPF_RESOURCE_PR24,
    IPF_RESOURCE_PR25,
    IPF_RESOURCE_PR26,
    IPF_RESOURCE_PR27,
    IPF_RESOURCE_PR28,
    IPF_RESOURCE_PR29,
    IPF_RESOURCE_PR30,
    IPF_RESOURCE_PR31,
    IPF_RESOURCE_PR32,
    IPF_RESOURCE_PR33,
    IPF_RESOURCE_PR34,
    IPF_RESOURCE_PR35,
    IPF_RESOURCE_PR36,
    IPF_RESOURCE_PR37,
    IPF_RESOURCE_PR38,
    IPF_RESOURCE_PR39,
    IPF_RESOURCE_PR40,
    IPF_RESOURCE_PR41,
    IPF_RESOURCE_PR42,
    IPF_RESOURCE_PR43,
    IPF_RESOURCE_PR44,
    IPF_RESOURCE_PR45,
    IPF_RESOURCE_PR46,
    IPF_RESOURCE_PR47,
    IPF_RESOURCE_PR48,
    IPF_RESOURCE_PR49,
    IPF_RESOURCE_PR50,
    IPF_RESOURCE_PR51,
    IPF_RESOURCE_PR52,
    IPF_RESOURCE_PR53,
    IPF_RESOURCE_PR54,
    IPF_RESOURCE_PR55,
    IPF_RESOURCE_PR56,
    IPF_RESOURCE_PR57,
    IPF_RESOURCE_PR58,
    IPF_RESOURCE_PR59,
    IPF_RESOURCE_PR60,
    IPF_RESOURCE_PR61,
    IPF_RESOURCE_PR62,
    IPF_RESOURCE_PR63,
    IPF_RESOURCE_BR0,
    IPF_RESOURCE_BR1,
    IPF_RESOURCE_BR2,
    IPF_RESOURCE_BR3,
    IPF_RESOURCE_BR4,
    IPF_RESOURCE_BR5,
    IPF_RESOURCE_BR6,
    IPF_RESOURCE_BR7,
    IPF_RESOURCE_PR,       /* Represents PR1-PR63  */  
    IPF_RESOURCE_PR_ROT,    /* Represents PR16-PR63 */
    IPF_RESOURCE_CR0,
    IPF_RESOURCE_CR1,
    IPF_RESOURCE_CR2,
    IPF_RESOURCE_CR3,
    IPF_RESOURCE_CR4,
    IPF_RESOURCE_CR5,
    IPF_RESOURCE_CR6,
    IPF_RESOURCE_CR7,
    IPF_RESOURCE_CR8,
    IPF_RESOURCE_CR9,
    IPF_RESOURCE_CR10,
    IPF_RESOURCE_CR11,
    IPF_RESOURCE_CR12,
    IPF_RESOURCE_CR13,
    IPF_RESOURCE_CR14,
    IPF_RESOURCE_CR15,
    IPF_RESOURCE_CR16,
    IPF_RESOURCE_CR17,
    IPF_RESOURCE_CR18,
    IPF_RESOURCE_CR19,
    IPF_RESOURCE_CR20,
    IPF_RESOURCE_CR21,
    IPF_RESOURCE_CR22,
    IPF_RESOURCE_CR23,
    IPF_RESOURCE_CR24,
    IPF_RESOURCE_CR25,
    IPF_RESOURCE_CR26,
    IPF_RESOURCE_CR27,
    IPF_RESOURCE_CR28,
    IPF_RESOURCE_CR29,
    IPF_RESOURCE_CR30,
    IPF_RESOURCE_CR31,
    IPF_RESOURCE_CR32,
    IPF_RESOURCE_CR33,
    IPF_RESOURCE_CR34,
    IPF_RESOURCE_CR35,
    IPF_RESOURCE_CR36,
    IPF_RESOURCE_CR37,
    IPF_RESOURCE_CR38,
    IPF_RESOURCE_CR39,
    IPF_RESOURCE_CR40,
    IPF_RESOURCE_CR41,
    IPF_RESOURCE_CR42,
    IPF_RESOURCE_CR43,
    IPF_RESOURCE_CR44,
    IPF_RESOURCE_CR45,
    IPF_RESOURCE_CR46,
    IPF_RESOURCE_CR47,
    IPF_RESOURCE_CR48,
    IPF_RESOURCE_CR49,
    IPF_RESOURCE_CR50,
    IPF_RESOURCE_CR51,
    IPF_RESOURCE_CR52,
    IPF_RESOURCE_CR53,
    IPF_RESOURCE_CR54,
    IPF_RESOURCE_CR55,
    IPF_RESOURCE_CR56,
    IPF_RESOURCE_CR57,
    IPF_RESOURCE_CR58,
    IPF_RESOURCE_CR59,
    IPF_RESOURCE_CR60,
    IPF_RESOURCE_CR61,
    IPF_RESOURCE_CR62,
    IPF_RESOURCE_CR63,
    IPF_RESOURCE_CR64,
    IPF_RESOURCE_CR65,
    IPF_RESOURCE_CR66,
    IPF_RESOURCE_CR67,
    IPF_RESOURCE_CR68,
    IPF_RESOURCE_CR69,
    IPF_RESOURCE_CR70,
    IPF_RESOURCE_CR71,
    IPF_RESOURCE_CR72,
    IPF_RESOURCE_CR73,
    IPF_RESOURCE_CR74,
    IPF_RESOURCE_CR75,
    IPF_RESOURCE_CR76,
    IPF_RESOURCE_CR77,
    IPF_RESOURCE_CR78,
    IPF_RESOURCE_CR79,
    IPF_RESOURCE_CR80,
    IPF_RESOURCE_CR81,
    IPF_RESOURCE_CR82,
    IPF_RESOURCE_CR83,
    IPF_RESOURCE_CR84,
    IPF_RESOURCE_CR85,
    IPF_RESOURCE_CR86,
    IPF_RESOURCE_CR87,
    IPF_RESOURCE_CR88,
    IPF_RESOURCE_CR89,
    IPF_RESOURCE_CR90,
    IPF_RESOURCE_CR91,
    IPF_RESOURCE_CR92,
    IPF_RESOURCE_CR93,
    IPF_RESOURCE_CR94,
    IPF_RESOURCE_CR95,
    IPF_RESOURCE_CR96,
    IPF_RESOURCE_CR97,
    IPF_RESOURCE_CR98,
    IPF_RESOURCE_CR99,
    IPF_RESOURCE_CR100,
    IPF_RESOURCE_CR101,
    IPF_RESOURCE_CR102,
    IPF_RESOURCE_CR103,
    IPF_RESOURCE_CR104,
    IPF_RESOURCE_CR105,
    IPF_RESOURCE_CR106,
    IPF_RESOURCE_CR107,
    IPF_RESOURCE_CR108,
    IPF_RESOURCE_CR109,
    IPF_RESOURCE_CR110,
    IPF_RESOURCE_CR111,
    IPF_RESOURCE_CR112,
    IPF_RESOURCE_CR113,
    IPF_RESOURCE_CR114,
    IPF_RESOURCE_CR115,
    IPF_RESOURCE_CR116,
    IPF_RESOURCE_CR117,
    IPF_RESOURCE_CR118,
    IPF_RESOURCE_CR119,
    IPF_RESOURCE_CR120,
    IPF_RESOURCE_CR121,
    IPF_RESOURCE_CR122,
    IPF_RESOURCE_CR123,
    IPF_RESOURCE_CR124,
    IPF_RESOURCE_CR125,
    IPF_RESOURCE_CR126,
    IPF_RESOURCE_CR127,
    IPF_RESOURCE_IP,  
    IPF_RESOURCE_AR_FPSR_SF0_FLAGS,
    IPF_RESOURCE_AR_FPSR_SF0_CONTROLS,    
    IPF_RESOURCE_AR_FPSR_SF1_FLAGS,
    IPF_RESOURCE_AR_FPSR_SF1_CONTROLS,
    IPF_RESOURCE_AR_FPSR_SF2_FLAGS,
    IPF_RESOURCE_AR_FPSR_SF2_CONTROLS,
    IPF_RESOURCE_AR_FPSR_SF3_FLAGS,
    IPF_RESOURCE_AR_FPSR_SF3_CONTROLS,
    IPF_RESOURCE_AR_FPSR_RV,
    IPF_RESOURCE_AR_FPSR_TRAPS,
    IPF_RESOURCE_PSR_PSR,  /* Represents all the PSR bits */
    IPF_RESOURCE_PSR_L,    /* Represents low PSR bits */ 
    IPF_RESOURCE_PSR_SM,   /* Represents PSR system mask bits */
    IPF_RESOURCE_PSR_UM,
/* the enumerations below are and should ALWAYS
   be ordered like they are ordered in the "real" PSR register. */
    
    IPF_RESOURCE_PSR_BE,
    IPF_RESOURCE_PSR_UP,
    IPF_RESOURCE_PSR_AC,
    IPF_RESOURCE_PSR_MFL,
    IPF_RESOURCE_PSR_MFH,
    IPF_RESOURCE_PSR_IC,
    IPF_RESOURCE_PSR_I,
    IPF_RESOURCE_PSR_PK,
    
    IPF_RESOURCE_PSR_DT,
    
    IPF_RESOURCE_PSR_DFL,
    IPF_RESOURCE_PSR_DFH,
    IPF_RESOURCE_PSR_SP,
    IPF_RESOURCE_PSR_PP,
    IPF_RESOURCE_PSR_DI,
    IPF_RESOURCE_PSR_SI,
    IPF_RESOURCE_PSR_DB,
    IPF_RESOURCE_PSR_LP,
    IPF_RESOURCE_PSR_TB,
    IPF_RESOURCE_PSR_RT,
    IPF_RESOURCE_PSR_CPL,
    IPF_RESOURCE_PSR_IS,
    IPF_RESOURCE_PSR_MC,
    IPF_RESOURCE_PSR_IT,
    IPF_RESOURCE_PSR_ID,
    IPF_RESOURCE_PSR_DA,
    IPF_RESOURCE_PSR_DD,
    IPF_RESOURCE_PSR_SS,
    IPF_RESOURCE_PSR_RI,
    IPF_RESOURCE_PSR_ED,
    IPF_RESOURCE_PSR_BN,
    IPF_RESOURCE_PSR_IA,
    IPF_RESOURCE_PSR_MF,  
    IPF_RESOURCE_PSR_DF,  
    IPF_RESOURCE_CFM,
    IPF_RESOURCE_ITC,
    IPF_RESOURCE_DTC,
    IPF_RESOURCE_ITR,
    IPF_RESOURCE_DTR,
    IPF_RESOURCE_ITC_LIMIT,
    IPF_RESOURCE_DTC_LIMIT,
    IPF_RESOURCE_InService,
    IPF_RESOURCE_PMC,
    IPF_RESOURCE_PMD,
    IPF_RESOURCE_PKR,
    IPF_RESOURCE_RR,
    IPF_RESOURCE_IBR,
    IPF_RESOURCE_DBR,
    IPF_RESOURCE_MSR,
    IPF_RESOURCE_CPUID,
    IPF_RESOURCE_AR_UNAT0,
    IPF_RESOURCE_AR_UNAT1,
    IPF_RESOURCE_AR_UNAT2,
    IPF_RESOURCE_AR_UNAT3,
    IPF_RESOURCE_AR_UNAT4,
    IPF_RESOURCE_AR_UNAT5,
    IPF_RESOURCE_AR_UNAT6,
    IPF_RESOURCE_AR_UNAT7,
    IPF_RESOURCE_AR_UNAT8,
    IPF_RESOURCE_AR_UNAT9,
    IPF_RESOURCE_AR_UNAT10,
    IPF_RESOURCE_AR_UNAT11,
    IPF_RESOURCE_AR_UNAT12,
    IPF_RESOURCE_AR_UNAT13,
    IPF_RESOURCE_AR_UNAT14,
    IPF_RESOURCE_AR_UNAT15,
    IPF_RESOURCE_AR_UNAT16,
    IPF_RESOURCE_AR_UNAT17,
    IPF_RESOURCE_AR_UNAT18,
    IPF_RESOURCE_AR_UNAT19,
    IPF_RESOURCE_AR_UNAT20,
    IPF_RESOURCE_AR_UNAT21,
    IPF_RESOURCE_AR_UNAT22,
    IPF_RESOURCE_AR_UNAT23,
    IPF_RESOURCE_AR_UNAT24,
    IPF_RESOURCE_AR_UNAT25,
    IPF_RESOURCE_AR_UNAT26,
    IPF_RESOURCE_AR_UNAT27,
    IPF_RESOURCE_AR_UNAT28,
    IPF_RESOURCE_AR_UNAT29,
    IPF_RESOURCE_AR_UNAT30,
    IPF_RESOURCE_AR_UNAT31,
    IPF_RESOURCE_AR_UNAT32,
    IPF_RESOURCE_AR_UNAT33,
    IPF_RESOURCE_AR_UNAT34,
    IPF_RESOURCE_AR_UNAT35,
    IPF_RESOURCE_AR_UNAT36,
    IPF_RESOURCE_AR_UNAT37,
    IPF_RESOURCE_AR_UNAT38,
    IPF_RESOURCE_AR_UNAT39,
    IPF_RESOURCE_AR_UNAT40,
    IPF_RESOURCE_AR_UNAT41,
    IPF_RESOURCE_AR_UNAT42,
    IPF_RESOURCE_AR_UNAT43,
    IPF_RESOURCE_AR_UNAT44,
    IPF_RESOURCE_AR_UNAT45,
    IPF_RESOURCE_AR_UNAT46,
    IPF_RESOURCE_AR_UNAT47,
    IPF_RESOURCE_AR_UNAT48,
    IPF_RESOURCE_AR_UNAT49,
    IPF_RESOURCE_AR_UNAT50,
    IPF_RESOURCE_AR_UNAT51,
    IPF_RESOURCE_AR_UNAT52,
    IPF_RESOURCE_AR_UNAT53,
    IPF_RESOURCE_AR_UNAT54,
    IPF_RESOURCE_AR_UNAT55,
    IPF_RESOURCE_AR_UNAT56,
    IPF_RESOURCE_AR_UNAT57,
    IPF_RESOURCE_AR_UNAT58,
    IPF_RESOURCE_AR_UNAT59,
    IPF_RESOURCE_AR_UNAT60,
    IPF_RESOURCE_AR_UNAT61,
    IPF_RESOURCE_AR_UNAT62,
    IPF_RESOURCE_AR_UNAT63,
  IPF_RESOURCE_RSE,
    IPF_RESOURCE_LAST,
    

    IPF_RESOURCE_AR_K0         =   IPF_RESOURCE_AR0+EM_AR_KR0,
    IPF_RESOURCE_AR_K1         =   IPF_RESOURCE_AR0+EM_AR_KR1,
    IPF_RESOURCE_AR_K2         =   IPF_RESOURCE_AR0+EM_AR_KR2,
    IPF_RESOURCE_AR_K3         =   IPF_RESOURCE_AR0+EM_AR_KR3,
    IPF_RESOURCE_AR_K4         =   IPF_RESOURCE_AR0+EM_AR_KR4,
    IPF_RESOURCE_AR_K5         =   IPF_RESOURCE_AR0+EM_AR_KR5,
    IPF_RESOURCE_AR_K6         =   IPF_RESOURCE_AR0+EM_AR_KR6,
    IPF_RESOURCE_AR_K7         =   IPF_RESOURCE_AR0+EM_AR_KR7,
    IPF_RESOURCE_AR_RSC        =   IPF_RESOURCE_AR0+EM_AR_RSC,
    IPF_RESOURCE_AR_BSP        =   IPF_RESOURCE_AR0+EM_AR_BSP,
    IPF_RESOURCE_AR_BSPSTORE   =   IPF_RESOURCE_AR0+EM_AR_BSPSTORE,
    IPF_RESOURCE_AR_RNAT       =   IPF_RESOURCE_AR0+EM_AR_RNAT,
      IPF_RESOURCE_AR_FCR       =   IPF_RESOURCE_AR0+EM_AR_FCR,
    IPF_RESOURCE_AR_EFLAG      =   IPF_RESOURCE_AR0+EM_AR_EFLAG,
    IPF_RESOURCE_AR_CSD        =   IPF_RESOURCE_AR0+EM_AR_CSD,
    IPF_RESOURCE_AR_SSD        =   IPF_RESOURCE_AR0+EM_AR_SSD,
    IPF_RESOURCE_AR_CFLG       =   IPF_RESOURCE_AR0+EM_AR_CFLG,
    IPF_RESOURCE_AR_FSR        =   IPF_RESOURCE_AR0+EM_AR_FSR,
    IPF_RESOURCE_AR_FIR        =   IPF_RESOURCE_AR0+EM_AR_FIR,
    IPF_RESOURCE_AR_FDR        =   IPF_RESOURCE_AR0+EM_AR_FDR,
    IPF_RESOURCE_AR_CCV        =   IPF_RESOURCE_AR0+EM_AR_CCV,
    IPF_RESOURCE_AR_UNAT       =   IPF_RESOURCE_AR0+EM_AR_UNAT, /* Represents ALL the unat bits */
    IPF_RESOURCE_AR_FPSR_FPSR  =   IPF_RESOURCE_AR0+EM_AR_FPSR,
    IPF_RESOURCE_AR_ITC        =   IPF_RESOURCE_AR0+EM_AR_ITC,
    IPF_RESOURCE_AR_PFS        =   IPF_RESOURCE_AR0+EM_AR_PFS,
    IPF_RESOURCE_AR_LC         =   IPF_RESOURCE_AR0+EM_AR_LC,
    IPF_RESOURCE_AR_EC         =   IPF_RESOURCE_AR0+EM_AR_EC,
 
    IPF_RESOURCE_CR_DCR    =    IPF_RESOURCE_CR0+EM_CR_DCR,
    IPF_RESOURCE_CR_ITM    =    IPF_RESOURCE_CR0+EM_CR_ITM,
    IPF_RESOURCE_CR_IVA    =    IPF_RESOURCE_CR0+EM_CR_IVA,
    IPF_RESOURCE_CR_PTA    =    IPF_RESOURCE_CR0+EM_CR_PTA,
    IPF_RESOURCE_CR_GPTA   =    IPF_RESOURCE_CR0+EM_CR_GPTA,
    IPF_RESOURCE_CR_IPSR   =    IPF_RESOURCE_CR0+EM_CR_IPSR,
    IPF_RESOURCE_CR_ISR    =    IPF_RESOURCE_CR0+EM_CR_ISR,
    IPF_RESOURCE_CR_IIP    =    IPF_RESOURCE_CR0+EM_CR_IIP,
    IPF_RESOURCE_CR_IFA    =    IPF_RESOURCE_CR0+EM_CR_IFA,
    IPF_RESOURCE_CR_ITIR   =    IPF_RESOURCE_CR0+EM_CR_ITIR,
    IPF_RESOURCE_CR_IIPA   =    IPF_RESOURCE_CR0+EM_CR_IIPA,
    IPF_RESOURCE_CR_IFS    =    IPF_RESOURCE_CR0+EM_CR_IFS,
    IPF_RESOURCE_CR_IIM    =    IPF_RESOURCE_CR0+EM_CR_IIM,
    IPF_RESOURCE_CR_IHA    =    IPF_RESOURCE_CR0+EM_CR_IHA,
    IPF_RESOURCE_CR_LID    =    IPF_RESOURCE_CR0+EM_CR_LID,
    IPF_RESOURCE_CR_IVR    =    IPF_RESOURCE_CR0+EM_CR_IVR,
    IPF_RESOURCE_CR_TPR    =    IPF_RESOURCE_CR0+EM_CR_TPR,
    IPF_RESOURCE_CR_EOI    =    IPF_RESOURCE_CR0+EM_CR_EOI,
    IPF_RESOURCE_CR_IRR0   =    IPF_RESOURCE_CR0+EM_CR_IRR0,
    IPF_RESOURCE_CR_IRR1   =    IPF_RESOURCE_CR0+EM_CR_IRR1,
    IPF_RESOURCE_CR_IRR2   =    IPF_RESOURCE_CR0+EM_CR_IRR2,
    IPF_RESOURCE_CR_IRR3   =    IPF_RESOURCE_CR0+EM_CR_IRR3,
    IPF_RESOURCE_CR_ITV    =    IPF_RESOURCE_CR0+EM_CR_ITV,
    IPF_RESOURCE_CR_PMV    =    IPF_RESOURCE_CR0+EM_CR_PMV,
    IPF_RESOURCE_CR_LRR0   =    IPF_RESOURCE_CR0+EM_CR_LRR0,
    IPF_RESOURCE_CR_LRR1   =    IPF_RESOURCE_CR0+EM_CR_LRR1,
    IPF_RESOURCE_CR_CMCV   =    IPF_RESOURCE_CR0+EM_CR_CMCV
} IPF_Resource_t;



#endif /* _IPF_RESOURCE_LIST_H_ */


/* ----------  End of IPF resources definition  ---------- */


/* ----------  Definition of Reg name extracted from decem.h  ---------- */

#ifndef EM_DECODER_H

typedef enum EM_decoder_reg_name
{
    EM_DECODER_NO_REG=0,
    EM_DECODER_REG_R0 = 98,
    EM_DECODER_REG_R1,
    EM_DECODER_REG_R2,
    EM_DECODER_REG_R3,
    EM_DECODER_REG_R4,
    EM_DECODER_REG_R5,
    EM_DECODER_REG_R6,
    EM_DECODER_REG_R7,
    EM_DECODER_REG_R8,
    EM_DECODER_REG_R9,
    EM_DECODER_REG_R10,
    EM_DECODER_REG_R11,
    EM_DECODER_REG_R12,
    EM_DECODER_REG_R13,
    EM_DECODER_REG_R14,
    EM_DECODER_REG_R15,
    EM_DECODER_REG_R16,
    EM_DECODER_REG_R17,
    EM_DECODER_REG_R18,
    EM_DECODER_REG_R19,
    EM_DECODER_REG_R20,
    EM_DECODER_REG_R21,
    EM_DECODER_REG_R22,
    EM_DECODER_REG_R23,
    EM_DECODER_REG_R24,
    EM_DECODER_REG_R25,
    EM_DECODER_REG_R26,
    EM_DECODER_REG_R27,
    EM_DECODER_REG_R28,
    EM_DECODER_REG_R29,
    EM_DECODER_REG_R30,
    EM_DECODER_REG_R31,
    EM_DECODER_REG_R32,
    EM_DECODER_REG_R33,
    EM_DECODER_REG_R34,
    EM_DECODER_REG_R35,
    EM_DECODER_REG_R36,
    EM_DECODER_REG_R37,
    EM_DECODER_REG_R38,
    EM_DECODER_REG_R39,
    EM_DECODER_REG_R40,
    EM_DECODER_REG_R41,
    EM_DECODER_REG_R42,
    EM_DECODER_REG_R43,
    EM_DECODER_REG_R44,
    EM_DECODER_REG_R45,
    EM_DECODER_REG_R46,
    EM_DECODER_REG_R47,
    EM_DECODER_REG_R48,
    EM_DECODER_REG_R49,
    EM_DECODER_REG_R50,
    EM_DECODER_REG_R51,
    EM_DECODER_REG_R52,
    EM_DECODER_REG_R53,
    EM_DECODER_REG_R54,
    EM_DECODER_REG_R55,
    EM_DECODER_REG_R56,
    EM_DECODER_REG_R57,
    EM_DECODER_REG_R58,
    EM_DECODER_REG_R59,
    EM_DECODER_REG_R60,
    EM_DECODER_REG_R61,
    EM_DECODER_REG_R62,
    EM_DECODER_REG_R63,
    EM_DECODER_REG_R64,
    EM_DECODER_REG_R65,
    EM_DECODER_REG_R66,
    EM_DECODER_REG_R67,
    EM_DECODER_REG_R68,
    EM_DECODER_REG_R69,
    EM_DECODER_REG_R70,
    EM_DECODER_REG_R71,
    EM_DECODER_REG_R72,
    EM_DECODER_REG_R73,
    EM_DECODER_REG_R74,
    EM_DECODER_REG_R75,
    EM_DECODER_REG_R76,
    EM_DECODER_REG_R77,
    EM_DECODER_REG_R78,
    EM_DECODER_REG_R79,
    EM_DECODER_REG_R80,
    EM_DECODER_REG_R81,
    EM_DECODER_REG_R82,
    EM_DECODER_REG_R83,
    EM_DECODER_REG_R84,
    EM_DECODER_REG_R85,
    EM_DECODER_REG_R86,
    EM_DECODER_REG_R87,
    EM_DECODER_REG_R88,
    EM_DECODER_REG_R89,
    EM_DECODER_REG_R90,
    EM_DECODER_REG_R91,
    EM_DECODER_REG_R92,
    EM_DECODER_REG_R93,
    EM_DECODER_REG_R94,
    EM_DECODER_REG_R95,
    EM_DECODER_REG_R96,
    EM_DECODER_REG_R97,
    EM_DECODER_REG_R98,
    EM_DECODER_REG_R99,
    EM_DECODER_REG_R100,
    EM_DECODER_REG_R101,
    EM_DECODER_REG_R102,
    EM_DECODER_REG_R103,
    EM_DECODER_REG_R104,
    EM_DECODER_REG_R105,
    EM_DECODER_REG_R106,
    EM_DECODER_REG_R107,
    EM_DECODER_REG_R108,
    EM_DECODER_REG_R109,
    EM_DECODER_REG_R110,
    EM_DECODER_REG_R111,
    EM_DECODER_REG_R112,
    EM_DECODER_REG_R113,
    EM_DECODER_REG_R114,
    EM_DECODER_REG_R115,
    EM_DECODER_REG_R116,
    EM_DECODER_REG_R117,
    EM_DECODER_REG_R118,
    EM_DECODER_REG_R119,
    EM_DECODER_REG_R120,
    EM_DECODER_REG_R121,
    EM_DECODER_REG_R122,
    EM_DECODER_REG_R123,
    EM_DECODER_REG_R124,
    EM_DECODER_REG_R125,
    EM_DECODER_REG_R126,
    EM_DECODER_REG_R127,
    EM_DECODER_REG_F0,
    EM_DECODER_REG_F1,
    EM_DECODER_REG_F2,
    EM_DECODER_REG_F3,
    EM_DECODER_REG_F4,
    EM_DECODER_REG_F5,
    EM_DECODER_REG_F6,
    EM_DECODER_REG_F7,
    EM_DECODER_REG_F8,
    EM_DECODER_REG_F9,
    EM_DECODER_REG_F10,
    EM_DECODER_REG_F11,
    EM_DECODER_REG_F12,
    EM_DECODER_REG_F13,
    EM_DECODER_REG_F14,
    EM_DECODER_REG_F15,
    EM_DECODER_REG_F16,
    EM_DECODER_REG_F17,
    EM_DECODER_REG_F18,
    EM_DECODER_REG_F19,
    EM_DECODER_REG_F20,
    EM_DECODER_REG_F21,
    EM_DECODER_REG_F22,
    EM_DECODER_REG_F23,
    EM_DECODER_REG_F24,
    EM_DECODER_REG_F25,
    EM_DECODER_REG_F26,
    EM_DECODER_REG_F27,
    EM_DECODER_REG_F28,
    EM_DECODER_REG_F29,
    EM_DECODER_REG_F30,
    EM_DECODER_REG_F31,
    EM_DECODER_REG_F32,
    EM_DECODER_REG_F33,
    EM_DECODER_REG_F34,
    EM_DECODER_REG_F35,
    EM_DECODER_REG_F36,
    EM_DECODER_REG_F37,
    EM_DECODER_REG_F38,
    EM_DECODER_REG_F39,
    EM_DECODER_REG_F40,
    EM_DECODER_REG_F41,
    EM_DECODER_REG_F42,
    EM_DECODER_REG_F43,
    EM_DECODER_REG_F44,
    EM_DECODER_REG_F45,
    EM_DECODER_REG_F46,
    EM_DECODER_REG_F47,
    EM_DECODER_REG_F48,
    EM_DECODER_REG_F49,
    EM_DECODER_REG_F50,
    EM_DECODER_REG_F51,
    EM_DECODER_REG_F52,
    EM_DECODER_REG_F53,
    EM_DECODER_REG_F54,
    EM_DECODER_REG_F55,
    EM_DECODER_REG_F56,
    EM_DECODER_REG_F57,
    EM_DECODER_REG_F58,
    EM_DECODER_REG_F59,
    EM_DECODER_REG_F60,
    EM_DECODER_REG_F61,
    EM_DECODER_REG_F62,
    EM_DECODER_REG_F63,
    EM_DECODER_REG_F64,
    EM_DECODER_REG_F65,
    EM_DECODER_REG_F66,
    EM_DECODER_REG_F67,
    EM_DECODER_REG_F68,
    EM_DECODER_REG_F69,
    EM_DECODER_REG_F70,
    EM_DECODER_REG_F71,
    EM_DECODER_REG_F72,
    EM_DECODER_REG_F73,
    EM_DECODER_REG_F74,
    EM_DECODER_REG_F75,
    EM_DECODER_REG_F76,
    EM_DECODER_REG_F77,
    EM_DECODER_REG_F78,
    EM_DECODER_REG_F79,
    EM_DECODER_REG_F80,
    EM_DECODER_REG_F81,
    EM_DECODER_REG_F82,
    EM_DECODER_REG_F83,
    EM_DECODER_REG_F84,
    EM_DECODER_REG_F85,
    EM_DECODER_REG_F86,
    EM_DECODER_REG_F87,
    EM_DECODER_REG_F88,
    EM_DECODER_REG_F89,
    EM_DECODER_REG_F90,
    EM_DECODER_REG_F91,
    EM_DECODER_REG_F92,
    EM_DECODER_REG_F93,
    EM_DECODER_REG_F94,
    EM_DECODER_REG_F95,
    EM_DECODER_REG_F96,
    EM_DECODER_REG_F97,
    EM_DECODER_REG_F98,
    EM_DECODER_REG_F99,
    EM_DECODER_REG_F100,
    EM_DECODER_REG_F101,
    EM_DECODER_REG_F102,
    EM_DECODER_REG_F103,
    EM_DECODER_REG_F104,
    EM_DECODER_REG_F105,
    EM_DECODER_REG_F106,
    EM_DECODER_REG_F107,
    EM_DECODER_REG_F108,
    EM_DECODER_REG_F109,
    EM_DECODER_REG_F110,
    EM_DECODER_REG_F111,
    EM_DECODER_REG_F112,
    EM_DECODER_REG_F113,
    EM_DECODER_REG_F114,
    EM_DECODER_REG_F115,
    EM_DECODER_REG_F116,
    EM_DECODER_REG_F117,
    EM_DECODER_REG_F118,
    EM_DECODER_REG_F119,
    EM_DECODER_REG_F120,
    EM_DECODER_REG_F121,
    EM_DECODER_REG_F122,
    EM_DECODER_REG_F123,
    EM_DECODER_REG_F124,
    EM_DECODER_REG_F125,
    EM_DECODER_REG_F126,
    EM_DECODER_REG_F127,
    EM_DECODER_REG_AR0,
    EM_DECODER_REG_AR1,
    EM_DECODER_REG_AR2,
    EM_DECODER_REG_AR3,
    EM_DECODER_REG_AR4,
    EM_DECODER_REG_AR5,
    EM_DECODER_REG_AR6,
    EM_DECODER_REG_AR7,
    EM_DECODER_REG_AR8,
    EM_DECODER_REG_AR9,
    EM_DECODER_REG_AR10,
    EM_DECODER_REG_AR11,
    EM_DECODER_REG_AR12,
    EM_DECODER_REG_AR13,
    EM_DECODER_REG_AR14,
    EM_DECODER_REG_AR15,
    EM_DECODER_REG_AR16,
    EM_DECODER_REG_AR17,
    EM_DECODER_REG_AR18,
    EM_DECODER_REG_AR19,
    EM_DECODER_REG_AR20,
    EM_DECODER_REG_AR21,
    EM_DECODER_REG_AR22,
    EM_DECODER_REG_AR23,
    EM_DECODER_REG_AR24,
    EM_DECODER_REG_AR25,
    EM_DECODER_REG_AR26,
    EM_DECODER_REG_AR27,
    EM_DECODER_REG_AR28,
    EM_DECODER_REG_AR29,
    EM_DECODER_REG_AR30,
    EM_DECODER_REG_AR31,
    EM_DECODER_REG_AR32,
    EM_DECODER_REG_AR33,
    EM_DECODER_REG_AR34,
    EM_DECODER_REG_AR35,
    EM_DECODER_REG_AR36,
    EM_DECODER_REG_AR37,
    EM_DECODER_REG_AR38,
    EM_DECODER_REG_AR39,
    EM_DECODER_REG_AR40,
    EM_DECODER_REG_AR41,
    EM_DECODER_REG_AR42,
    EM_DECODER_REG_AR43,
    EM_DECODER_REG_AR44,
    EM_DECODER_REG_AR45,
    EM_DECODER_REG_AR46,
    EM_DECODER_REG_AR47,
    EM_DECODER_REG_AR48,
    EM_DECODER_REG_AR49,
    EM_DECODER_REG_AR50,
    EM_DECODER_REG_AR51,
    EM_DECODER_REG_AR52,
    EM_DECODER_REG_AR53,
    EM_DECODER_REG_AR54,
    EM_DECODER_REG_AR55,
    EM_DECODER_REG_AR56,
    EM_DECODER_REG_AR57,
    EM_DECODER_REG_AR58,
    EM_DECODER_REG_AR59,
    EM_DECODER_REG_AR60,
    EM_DECODER_REG_AR61,
    EM_DECODER_REG_AR62,
    EM_DECODER_REG_AR63,
    EM_DECODER_REG_AR64,
    EM_DECODER_REG_AR65,
    EM_DECODER_REG_AR66,
    EM_DECODER_REG_AR67,
    EM_DECODER_REG_AR68,
    EM_DECODER_REG_AR69,
    EM_DECODER_REG_AR70,
    EM_DECODER_REG_AR71,
    EM_DECODER_REG_AR72,
    EM_DECODER_REG_AR73,
    EM_DECODER_REG_AR74,
    EM_DECODER_REG_AR75,
    EM_DECODER_REG_AR76,
    EM_DECODER_REG_AR77,
    EM_DECODER_REG_AR78,
    EM_DECODER_REG_AR79,
    EM_DECODER_REG_AR80,
    EM_DECODER_REG_AR81,
    EM_DECODER_REG_AR82,
    EM_DECODER_REG_AR83,
    EM_DECODER_REG_AR84,
    EM_DECODER_REG_AR85,
    EM_DECODER_REG_AR86,
    EM_DECODER_REG_AR87,
    EM_DECODER_REG_AR88,
    EM_DECODER_REG_AR89,
    EM_DECODER_REG_AR90,
    EM_DECODER_REG_AR91,
    EM_DECODER_REG_AR92,
    EM_DECODER_REG_AR93,
    EM_DECODER_REG_AR94,
    EM_DECODER_REG_AR95,
    EM_DECODER_REG_AR96,
    EM_DECODER_REG_AR97,
    EM_DECODER_REG_AR98,
    EM_DECODER_REG_AR99,
    EM_DECODER_REG_AR100,
    EM_DECODER_REG_AR101,
    EM_DECODER_REG_AR102,
    EM_DECODER_REG_AR103,
    EM_DECODER_REG_AR104,
    EM_DECODER_REG_AR105,
    EM_DECODER_REG_AR106,
    EM_DECODER_REG_AR107,
    EM_DECODER_REG_AR108,
    EM_DECODER_REG_AR109,
    EM_DECODER_REG_AR110,
    EM_DECODER_REG_AR111,
    EM_DECODER_REG_AR112,
    EM_DECODER_REG_AR113,
    EM_DECODER_REG_AR114,
    EM_DECODER_REG_AR115,
    EM_DECODER_REG_AR116,
    EM_DECODER_REG_AR117,
    EM_DECODER_REG_AR118,
    EM_DECODER_REG_AR119,
    EM_DECODER_REG_AR120,
    EM_DECODER_REG_AR121,
    EM_DECODER_REG_AR122,
    EM_DECODER_REG_AR123,
    EM_DECODER_REG_AR124,
    EM_DECODER_REG_AR125,
    EM_DECODER_REG_AR126,
    EM_DECODER_REG_AR127,
    EM_DECODER_REG_P0,
    EM_DECODER_REG_P1,
    EM_DECODER_REG_P2,
    EM_DECODER_REG_P3,
    EM_DECODER_REG_P4,
    EM_DECODER_REG_P5,
    EM_DECODER_REG_P6,
    EM_DECODER_REG_P7,
    EM_DECODER_REG_P8,
    EM_DECODER_REG_P9,
    EM_DECODER_REG_P10,
    EM_DECODER_REG_P11,
    EM_DECODER_REG_P12,
    EM_DECODER_REG_P13,
    EM_DECODER_REG_P14,
    EM_DECODER_REG_P15,
    EM_DECODER_REG_P16,
    EM_DECODER_REG_P17,
    EM_DECODER_REG_P18,
    EM_DECODER_REG_P19,
    EM_DECODER_REG_P20,
    EM_DECODER_REG_P21,
    EM_DECODER_REG_P22,
    EM_DECODER_REG_P23,
    EM_DECODER_REG_P24,
    EM_DECODER_REG_P25,
    EM_DECODER_REG_P26,
    EM_DECODER_REG_P27,
    EM_DECODER_REG_P28,
    EM_DECODER_REG_P29,
    EM_DECODER_REG_P30,
    EM_DECODER_REG_P31,
    EM_DECODER_REG_P32,
    EM_DECODER_REG_P33,
    EM_DECODER_REG_P34,
    EM_DECODER_REG_P35,
    EM_DECODER_REG_P36,
    EM_DECODER_REG_P37,
    EM_DECODER_REG_P38,
    EM_DECODER_REG_P39,
    EM_DECODER_REG_P40,
    EM_DECODER_REG_P41,
    EM_DECODER_REG_P42,
    EM_DECODER_REG_P43,
    EM_DECODER_REG_P44,
    EM_DECODER_REG_P45,
    EM_DECODER_REG_P46,
    EM_DECODER_REG_P47,
    EM_DECODER_REG_P48,
    EM_DECODER_REG_P49,
    EM_DECODER_REG_P50,
    EM_DECODER_REG_P51,
    EM_DECODER_REG_P52,
    EM_DECODER_REG_P53,
    EM_DECODER_REG_P54,
    EM_DECODER_REG_P55,
    EM_DECODER_REG_P56,
    EM_DECODER_REG_P57,
    EM_DECODER_REG_P58,
    EM_DECODER_REG_P59,
    EM_DECODER_REG_P60,
    EM_DECODER_REG_P61,
    EM_DECODER_REG_P62,
    EM_DECODER_REG_P63,
    EM_DECODER_REG_BR0 ,
    EM_DECODER_REG_BR1,
    EM_DECODER_REG_BR2,
    EM_DECODER_REG_BR3,
    EM_DECODER_REG_BR4,
    EM_DECODER_REG_BR5,
    EM_DECODER_REG_BR6,
    EM_DECODER_REG_BR7,
    EM_DECODER_REG_PR,
    EM_DECODER_REG_PR_ROT,
    EM_DECODER_REG_CR0,
    EM_DECODER_REG_CR1,
    EM_DECODER_REG_CR2,
    EM_DECODER_REG_CR3,
    EM_DECODER_REG_CR4,
    EM_DECODER_REG_CR5,
    EM_DECODER_REG_CR6,
    EM_DECODER_REG_CR7,
    EM_DECODER_REG_CR8,
    EM_DECODER_REG_CR9,
    EM_DECODER_REG_CR10,
    EM_DECODER_REG_CR11,
    EM_DECODER_REG_CR12,
    EM_DECODER_REG_CR13,
    EM_DECODER_REG_CR14,
    EM_DECODER_REG_CR15,
    EM_DECODER_REG_CR16,
    EM_DECODER_REG_CR17,
    EM_DECODER_REG_CR18,
    EM_DECODER_REG_CR19,
    EM_DECODER_REG_CR20,
    EM_DECODER_REG_CR21,
    EM_DECODER_REG_CR22,
    EM_DECODER_REG_CR23,
    EM_DECODER_REG_CR24,
    EM_DECODER_REG_CR25,
    EM_DECODER_REG_CR26,
    EM_DECODER_REG_CR27,
    EM_DECODER_REG_CR28,
    EM_DECODER_REG_CR29,
    EM_DECODER_REG_CR30,
    EM_DECODER_REG_CR31,
    EM_DECODER_REG_CR32,
    EM_DECODER_REG_CR33,
    EM_DECODER_REG_CR34,
    EM_DECODER_REG_CR35,
    EM_DECODER_REG_CR36,
    EM_DECODER_REG_CR37,
    EM_DECODER_REG_CR38,
    EM_DECODER_REG_CR39,
    EM_DECODER_REG_CR40,
    EM_DECODER_REG_CR41,
    EM_DECODER_REG_CR42,
    EM_DECODER_REG_CR43,
    EM_DECODER_REG_CR44,
    EM_DECODER_REG_CR45,
    EM_DECODER_REG_CR46,
    EM_DECODER_REG_CR47,
    EM_DECODER_REG_CR48,
    EM_DECODER_REG_CR49,
    EM_DECODER_REG_CR50,
    EM_DECODER_REG_CR51,
    EM_DECODER_REG_CR52,
    EM_DECODER_REG_CR53,
    EM_DECODER_REG_CR54,
    EM_DECODER_REG_CR55,
    EM_DECODER_REG_CR56,
    EM_DECODER_REG_CR57,
    EM_DECODER_REG_CR58,
    EM_DECODER_REG_CR59,
    EM_DECODER_REG_CR60,
    EM_DECODER_REG_CR61,
    EM_DECODER_REG_CR62,
    EM_DECODER_REG_CR63,
    EM_DECODER_REG_CR64,
    EM_DECODER_REG_CR65,
    EM_DECODER_REG_CR66,
    EM_DECODER_REG_CR67,
    EM_DECODER_REG_CR68,
    EM_DECODER_REG_CR69,
    EM_DECODER_REG_CR70,
    EM_DECODER_REG_CR71,
    EM_DECODER_REG_CR72,
    EM_DECODER_REG_CR73,
    EM_DECODER_REG_CR74,
    EM_DECODER_REG_CR75,
    EM_DECODER_REG_CR76,
    EM_DECODER_REG_CR77,
    EM_DECODER_REG_CR78,
    EM_DECODER_REG_CR79,
    EM_DECODER_REG_CR80,
    EM_DECODER_REG_CR81,
    EM_DECODER_REG_CR82,
    EM_DECODER_REG_CR83,
    EM_DECODER_REG_CR84,
    EM_DECODER_REG_CR85,
    EM_DECODER_REG_CR86,
    EM_DECODER_REG_CR87,
    EM_DECODER_REG_CR88,
    EM_DECODER_REG_CR89,
    EM_DECODER_REG_CR90,
    EM_DECODER_REG_CR91,
    EM_DECODER_REG_CR92,
    EM_DECODER_REG_CR93,
    EM_DECODER_REG_CR94,
    EM_DECODER_REG_CR95,
    EM_DECODER_REG_CR96,
    EM_DECODER_REG_CR97,
    EM_DECODER_REG_CR98,
    EM_DECODER_REG_CR99,
    EM_DECODER_REG_CR100,
    EM_DECODER_REG_CR101,
    EM_DECODER_REG_CR102,
    EM_DECODER_REG_CR103,
    EM_DECODER_REG_CR104,
    EM_DECODER_REG_CR105,
    EM_DECODER_REG_CR106,
    EM_DECODER_REG_CR107,
    EM_DECODER_REG_CR108,
    EM_DECODER_REG_CR109,
    EM_DECODER_REG_CR110,
    EM_DECODER_REG_CR111,
    EM_DECODER_REG_CR112,
    EM_DECODER_REG_CR113,
    EM_DECODER_REG_CR114,
    EM_DECODER_REG_CR115,
    EM_DECODER_REG_CR116,
    EM_DECODER_REG_CR117,
    EM_DECODER_REG_CR118,
    EM_DECODER_REG_CR119,
    EM_DECODER_REG_CR120,
    EM_DECODER_REG_CR121,
    EM_DECODER_REG_CR122,
    EM_DECODER_REG_CR123,
    EM_DECODER_REG_CR124,
    EM_DECODER_REG_CR125,
    EM_DECODER_REG_CR126,
    EM_DECODER_REG_CR127,
    EM_DECODER_REG_PSR,
    EM_DECODER_REG_PSR_L,
    EM_DECODER_REG_PSR_UM,
    EM_DECODER_REG_IP,      /* register IP name */ 
    EM_DECODER_EM_REG_LAST,

    EM_DECODER_REG_AR_K0   = EM_DECODER_REG_AR0+EM_AR_KR0,
    EM_DECODER_REG_AR_K1   = EM_DECODER_REG_AR0+EM_AR_KR1,
    EM_DECODER_REG_AR_K2   = EM_DECODER_REG_AR0+EM_AR_KR2,
    EM_DECODER_REG_AR_K3   = EM_DECODER_REG_AR0+EM_AR_KR3,
    EM_DECODER_REG_AR_K4   = EM_DECODER_REG_AR0+EM_AR_KR4, /* added AR_K4-7 */
    EM_DECODER_REG_AR_K5   = EM_DECODER_REG_AR0+EM_AR_KR5,
    EM_DECODER_REG_AR_K6   = EM_DECODER_REG_AR0+EM_AR_KR6,
    EM_DECODER_REG_AR_K7   = EM_DECODER_REG_AR0+EM_AR_KR7,
    EM_DECODER_REG_AR_RSC  = EM_DECODER_REG_AR0+EM_AR_RSC,
    EM_DECODER_REG_AR_BSP  = EM_DECODER_REG_AR0+EM_AR_BSP,
    EM_DECODER_REG_AR_BSPSTORE = EM_DECODER_REG_AR0+EM_AR_BSPSTORE,
    EM_DECODER_REG_AR_RNAT = EM_DECODER_REG_AR0+EM_AR_RNAT,
    EM_DECODER_REG_AR_EFLAG= EM_DECODER_REG_AR0+EM_AR_EFLAG,
    EM_DECODER_REG_AR_CSD  = EM_DECODER_REG_AR0+EM_AR_CSD,
    EM_DECODER_REG_AR_SSD  = EM_DECODER_REG_AR0+EM_AR_SSD,
    EM_DECODER_REG_AR_CFLG = EM_DECODER_REG_AR0+EM_AR_CFLG,
    EM_DECODER_REG_AR_FSR  = EM_DECODER_REG_AR0+EM_AR_FSR,
    EM_DECODER_REG_AR_FIR  = EM_DECODER_REG_AR0+EM_AR_FIR,
    EM_DECODER_REG_AR_FDR  = EM_DECODER_REG_AR0+EM_AR_FDR,
    EM_DECODER_REG_AR_CCV  = EM_DECODER_REG_AR0+EM_AR_CCV,
    EM_DECODER_REG_AR_UNAT = EM_DECODER_REG_AR0+EM_AR_UNAT,
    EM_DECODER_REG_AR_FPSR = EM_DECODER_REG_AR0+EM_AR_FPSR,
    EM_DECODER_REG_AR_ITC  = EM_DECODER_REG_AR0+EM_AR_ITC,  
    EM_DECODER_REG_AR_PFS  = EM_DECODER_REG_AR0+EM_AR_PFS,
    EM_DECODER_REG_AR_LC   = EM_DECODER_REG_AR0+EM_AR_LC,
    EM_DECODER_REG_AR_EC   = EM_DECODER_REG_AR0+EM_AR_EC,

    EM_DECODER_REG_CR_DCR  = EM_DECODER_REG_CR0+EM_CR_DCR,
    EM_DECODER_REG_CR_ITM  = EM_DECODER_REG_CR0+EM_CR_ITM,
    EM_DECODER_REG_CR_IVA  = EM_DECODER_REG_CR0+EM_CR_IVA,
    EM_DECODER_REG_CR_PTA  = EM_DECODER_REG_CR0+EM_CR_PTA,
    EM_DECODER_REG_CR_GPTA = EM_DECODER_REG_CR0+EM_CR_GPTA,
    EM_DECODER_REG_CR_IPSR = EM_DECODER_REG_CR0+EM_CR_IPSR,
    EM_DECODER_REG_CR_ISR  = EM_DECODER_REG_CR0+EM_CR_ISR,
    EM_DECODER_REG_CR_IIP  = EM_DECODER_REG_CR0+EM_CR_IIP,
    EM_DECODER_REG_CR_IFA  = EM_DECODER_REG_CR0+EM_CR_IFA,
    EM_DECODER_REG_CR_ITIR = EM_DECODER_REG_CR0+EM_CR_ITIR,
    EM_DECODER_REG_CR_IIPA = EM_DECODER_REG_CR0+EM_CR_IIPA,
    EM_DECODER_REG_CR_IFS  = EM_DECODER_REG_CR0+EM_CR_IFS,
    EM_DECODER_REG_CR_IIM  = EM_DECODER_REG_CR0+EM_CR_IIM,
    EM_DECODER_REG_CR_IHA  = EM_DECODER_REG_CR0+EM_CR_IHA,

    EM_DECODER_REG_CR_LID  = EM_DECODER_REG_CR0+EM_CR_LID,
    EM_DECODER_REG_CR_IVR  = EM_DECODER_REG_CR0+EM_CR_IVR,
    EM_DECODER_REG_CR_TPR  = EM_DECODER_REG_CR0+EM_CR_TPR,
    EM_DECODER_REG_CR_EOI  = EM_DECODER_REG_CR0+EM_CR_EOI,
    EM_DECODER_REG_CR_IRR0 = EM_DECODER_REG_CR0+EM_CR_IRR0,
    EM_DECODER_REG_CR_IRR1 = EM_DECODER_REG_CR0+EM_CR_IRR1,
    EM_DECODER_REG_CR_IRR2 = EM_DECODER_REG_CR0+EM_CR_IRR2,
    EM_DECODER_REG_CR_IRR3 = EM_DECODER_REG_CR0+EM_CR_IRR3,
    EM_DECODER_REG_CR_ITV  = EM_DECODER_REG_CR0+EM_CR_ITV,
    EM_DECODER_REG_CR_PMV  = EM_DECODER_REG_CR0+EM_CR_PMV,
    EM_DECODER_REG_CR_LRR0 = EM_DECODER_REG_CR0+EM_CR_LRR0,
    EM_DECODER_REG_CR_LRR1 = EM_DECODER_REG_CR0+EM_CR_LRR1,
    EM_DECODER_REG_CR_CMCV = EM_DECODER_REG_CR0+EM_CR_CMCV,
        
/************************************************************/
    EM_DECODER_REG_LAST
} EM_Decoder_Reg_Name;

#define EM_DECODER_BIT_CYCLE_BREAK 0x10000 /*Inst is last in its group */




#endif /* EM_DECODER_H */

/* ----------  End of Reg name definition  ---------- */

